tgsi: allow dfracexp second dst to be in any channel
st/glsl: use uvec4 for native integer any

Not 100% sure on this but I think FSNE, DSNE and USNE all
return unsigned ints.
nvc0/ir: add emission of dadd/dmul/dmad opcodes, fix minmax

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
nvc0/ir: fix lowering of RSQ/RCP/SQRT/MOD to work with F64

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
HACK nvc0/ir: populate shader header bit indicating fp64

HACK ALERT: this should figure out if the shader's doing fp64 stuff and
use that to populate the header.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
nvc0/ir: no instruction can load a double immediate

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
nvc0/ir: add support for new TGSI double opcodes

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
temporarily claim to have sqrt
nvc0/ir: remove merge/split pairs to allow normal propagation to occur

Because the TGSI interface creates merges for each instruction source
and then splits them back out, there are a lot of unnecessary
merge/split pairs which do essentially nothing. The various modifier/etc
propagation doesn't know how to walk though those, so just remove them
when they're unnecessary.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
nvc0/ir: handle zero and negative sqrt arguments

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
nv50/ir: fix hard-coded TYPE_U32 sized register

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
nv50/ir: fix phi sources when a phi def has been merged

In a situation where double-register values are used, the phi nodes can
still end up being u32 values. They all get merged into one RA node
though. When fixing up the merge (which comes after the phi node), the
phi node's def would get fixed, but not its sources which would remain
at the low register value.

This maintains the invariant that a phi node's defs and sources are
allocated the same register.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
glsl: add a lowering pass for frexp with double arguments

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
nvc0: make sure that the local memory allocation is aligned to 0x10

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>