drivers/iio/adc/ad9361: Revise RFPLL and BPBLL reference sale behavior

Fix BBPLL max PFD frequency (70MHz)
Default use reference doubler if the ext ref is <= 40MHz (previous < 40MHz)
This can cause more fractional spurs but will give better phase noise
performance. If you like to revert to the previous behavior you
can set: adi,trx-synthesizer-target-fref-overwrite-hz = <40000000>;
This will ensure that the scaled reference clock for RFPLL will never
exceed this value.
You may also use this property to further downscale the target
reference clock.

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>