MP: Registers and state definitions for I/O APIC, which routes
interrupts from I/O devices onto the APIC bus.
MP: registers and variable definitions for the Local APIC, which sits
between the APIC bus and the processor, and does a bunch of useful
things in an MP system:
 - accepts APIC bus interrupt requests and passes the interrupt vector
   to the processor
 - manages the processor's interrupt priority.
 - initiates priority-based software interrupts directed at this or
   other processors

it also includes a local countdown timer and a few other functions.
Primitives for a few atomic operations.
Declarations of of cpu_simple_*lock* functions.
(currently not inlined, for debuggability)
stuff shared between local and i/o apic drivers.
(some) per-CPU state.
"register" definitions for the Intel MP BIOS (spec rev 1.4).

These data structures are defined by the BIOS and are read by our MP
BIOS driver to figure out the configuration of a multiprocessor PC.
MP BIOS support, including some of the interrupt-routing data
structures built after parsing the MP BIOS information.
APIC interrupt handler stubs.
Main I/O APIC driver and interrupt registration bits.
Local APIC driver.
Includes variant DELAY and microtime implementations using the local
APIC timer.
Aux. processor spinup trampoline code.
Functions shared between local and i/o apic drivers.
cpu_simple_*lock* implementation.
For now, not inlined for debugging.
CPU driver (handles identification and configuration, and spinup of
secondary CPUs).
MP BIOS "driver".  Logically part of mainbus.

Attempt to locate MP configuration table; if found, configure CPU's
and I/O apic's, and record interrupt routing information for
subsequent interrupt handler registration.
Inter-Processor Interrupt dispatching.
MP: include cpu_info structure, which picks up what used to be in
several global variables.
XXX cpu_info is bigger than it should be..
MP: MP-safe and APIC-friendly spl*/splx() implementation.

Keep spl state as a level, rather than interrupt mask, since on
multiple APIC systems there may be more interrupt lines than can fit
in a single 32-bit word.

Interrupt levels are now compatible with the APIC priority scheme
(high order 4 bits of the IDT vector number).
Bump MSGBUFSIZE since mp_verbose is pretty verbose.