Defines cleanup
Fix store_scat hang

If the mask was clear for a lane, but the lane was not present in the cache, it would
trigger a cache miss, but would load the cache line as readable, not writable. This
would result in an infinite loop where it repeatedly attempted to write invalidate the
line.

It should not have triggered a cache miss. Ignore memory requests if the mask bit is
clear. Don't qualify store by the mask bit.