[pymtl.tools] add hacky VCD tracing implementation + tests
[pymtl.tools] significant simplification of VCD code
[pymtl.tools] trigger VCD per net, not per signal (details)

Previously had a unique VCD symbol per signal (port/wire), even though
interconnected signals always had the same value.  Changed this logic to
only report value changes per net, rather than per signal.

In addition to improving performance, this should fix a crash caused by
greenlets enabled models not being able to serialize the attribute
net._DEBUG_signal_names.
[pymtl.tools] VCD refactored to be fully self-contained (details)

Previous design always had coupling between the SimulationTool and the VCD
generation logic. Now the SimulationTool is completely independent of VCD
logic (other than the dump_vcd() method).  The VCD logic when enable
simply monkey-patches the simulator after it has been constructed to
enable VCD output.
[pymtl.tools] name mangle signal lists for gtkwave
[pymtl] add get_vcd_filename() helper for testing
[labs,examples] use get_vcd_filename()
[accel] use get_vcd_filename()
[pclib] use get_vcd_filename()
[travis] add --dump-vcd tests to travis
[mem] use get_vcd_filename()
[accel] fix syntax error
[pymtl] get_vcd_filename() generates fully qualified name
[net] use get_vcd_filename(), add __init__.py
[pymtl] more updating of test vcd output names
[proc] use get_vcd_filename()
[pymtl.tools] verilator VCD dump w some bugs (details)

Verilator VCD dump is working with the following caveats:

- To enable VCD dumping, a vcd_dump flag must be passed to the
  get_verilated() function.

- The VCD file will not be generated successfully unless destroy_model()
  is called on the verilated model. While this is **supposed** to happen
  automatically when the model goes out of scope, in practice this needs
  to be called explicitly like so:

    model._model.destroy_model()

  Fixing this is a priority.

- Value changes generated by Verilator have a half-cycle delay when
  compared to their Python counterparts. This means updates appear on the
  falling edge of the clock instead of the rising edge. Fixing this is
  another priority item.
[pymtl.tools] changes to Verilator driver, fails some tests
[pymtl.tools] revert some changes to Verilator driver, fix later
[net] fix typo in MeshRouterRTL_test