testbench made, and 10011110-01111111 doesn't equal 00011111 as it should.
Fixed issue by assigning register in the idle state. Also, other problems have been solved by making the simulation run for the required 600 clock periods. Fractional section still to be implemented, but so far so good - I got a 2 out with a 2 put in.
Merge branch 'master' of https://github.com/DUDE-FPGA/Calculator