1) re-factoring of division code to be closer to other (already re-factored) fpu modules
2) complete re-design for float<->integer converters

Next planned efforts:
a) make some pre/post operation stages (like input analysis or result rounding) to be shared across whole FPU
b) implement Goldschmidth's algorithm for division
c) share HW-multiplier for mul&div modules (perhaps the mul/div will be combined in the way similar to add/sub)