lit: Don't use python 2.6 features

LLVM supports python 2.5, this fixes a (somewhat) recent regression.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223626 91177308-0d34-0410-b5e6-96231b3b80d8
X86 intrinsics moved form X86ISelLowering.cpp to X86IntrinsicsInfo.h
X86ISelLowering.cpp has a long switch for intrinsics. I moved a part of
this long switch to the new intrinsics table in X86IntrinsicsInfo.h.
No functional changes, just code and compile time optimization.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223641 91177308-0d34-0410-b5e6-96231b3b80d8
Removal Of Duplicate Test Case from shift.ll file


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223648 91177308-0d34-0410-b5e6-96231b3b80d8
Move materialize/Dematerialize calls to linkFunctionBody. NFC.

Just less code duplication.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223653 91177308-0d34-0410-b5e6-96231b3b80d8
Simple style fixes.

* Use a range loop.
* Move simple continue checks earlier.
* clang-format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223654 91177308-0d34-0410-b5e6-96231b3b80d8
[CMake] Fix installation of llvm-ranlib on multiconfig builder.

Introduce install_symlink.cmake from clang/tools/driver/clang_symlink.cmake.

FIXME: Would it be generalized?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223655 91177308-0d34-0410-b5e6-96231b3b80d8
Fix linking of prologue data.

It would crash when the function was lazy linked.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223656 91177308-0d34-0410-b5e6-96231b3b80d8
Use range loops. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223657 91177308-0d34-0410-b5e6-96231b3b80d8
Use range loops. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223658 91177308-0d34-0410-b5e6-96231b3b80d8
Move the ValueMap lookup inside linkFunctionBody. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223659 91177308-0d34-0410-b5e6-96231b3b80d8
[X86] Improved lowering of packed v8i16 vector shifts by non-constant count.

Before this patch, the backend sub-optimally expanded the non-constant shift
count of a v8i16 shift into a sequence of two 'movd' plus 'movzwl'.

With this patch the backend checks if the target features sse4.1. If so, then
it lets the shuffle legalizer deal with the expansion of the shift amount.

Example:
;;
define <8 x i16> @test(<8 x i16> %A, <8 x i16> %B) {
  %shamt = shufflevector <8 x i16> %B, <8 x i16> undef, <8 x i32> zeroinitializer
  %shl = shl <8 x i16> %A, %shamt
  ret <8 x i16> %shl
}
;;

Before (with -mattr=+avx):
  vmovd  %xmm1, %eax
  movzwl  %ax, %eax
  vmovd  %eax, %xmm1
  vpsllw  %xmm1, %xmm0, %xmm0
  retq

Now:
  vpxor  %xmm2, %xmm2, %xmm2
  vpblendw  $1, %xmm1, %xmm2, %xmm1
  vpsllw  %xmm1, %xmm0, %xmm0
  retq


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223660 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Add Mips-specific CCIf's for accessing the MipsCCState. NFC.

Reviewers: vmedic

Reviewed By: vmedic

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6213

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223662 91177308-0d34-0410-b5e6-96231b3b80d8
Use CHECK-DAG to reduce the noise in an upcoming patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223663 91177308-0d34-0410-b5e6-96231b3b80d8
[Hexagon] Adding packhl instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223664 91177308-0d34-0410-b5e6-96231b3b80d8
Simplify test. NFC.

This is just testing the largest merge mode for comdats. No need to use
hard to read names and fancy types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223665 91177308-0d34-0410-b5e6-96231b3b80d8
Simplify the test. NFC.

Since the main file was empty, we can just copy the content of the Input file
into it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223666 91177308-0d34-0410-b5e6-96231b3b80d8
[Hexagon] Adding combine reg, reg with predicated forms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223667 91177308-0d34-0410-b5e6-96231b3b80d8
[X86] Improved tablegen patters for matching TZCNT/LZCNT.

Teach ISel how to match a TZCNT/LZCNT from a conditional move if the
condition code is X86_COND_NE.
Existing tablegen patterns only allowed to match TZCNT/LZCNT from a
X86cond with condition code equal to X86_COND_E. To avoid introducing
extra rules, I added an 'ImmLeaf' definition that checks if the
condition code is COND_E or COND_NE.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223668 91177308-0d34-0410-b5e6-96231b3b80d8
AArch64: treat HFAs containing "half" types as blocks too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223669 91177308-0d34-0410-b5e6-96231b3b80d8
Fix the JIT code for the Kaleidoscope tutorial.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223670 91177308-0d34-0410-b5e6-96231b3b80d8