ilo: simplify ilo_texture_set_slice_flags()

Call ilo_texture_get_slice() for the last slice so that we can get rid of the
duplicated assert().
ilo: fix a HiZ bo leakage

Dereference the HiZ bo when the texture is destroyed.
ilo: OOM for HiZ is fatal on GEN6

On GEN6, HiZ and Separate Stencil Buffer must be enabled at the same time.
ilo: use HALIGN_4 on GEN7 for depth buffers

The comment was no longer true since 6642381e7513926b847d6bc10bf590e1c0c54859.
ilo: emit gen7_wa_pipe_control_wm_max_threads_stall on Haswell

Rename the workaround, as it is for 3DSTATE_PS instead of 3DSTATE_WM, and emit
it on Haswell too.

This does not fix any app, but an assertion failure.
ilo: decide on hiz first in texture allocation

Add tex_layout_init_hiz() before tex_layout_init_format() to decide whether
HiZ should be enabled.

On GEN6, because of layer offsetting, HiZ is enabled only when the texture is
non-mipmapped and non-array.  PIPE_USAGE_STAGING is also taken as a hint to
disable HiZ.
ilo: use a helper to determine if HiZ is enabled

Add ilo_texture_can_enable_hiz and replace all checks for tex->hiz.bo by calls
to ilo_texture_can_enable_hiz().
ilo: disable HiZ for misaligned levels

We need to disable HiZ for non-8x4 aligned levels, except for level 0, layer
0.  For the very first layer we can adjust Width and Height fields of
3DSTATE_DEPTH_BUFFER to make it aligned.

Specifically, add ILO_TEXTURE_HIZ and set the flag only for properly aligned
levels.  ilo_texture_can_enable_hiz() is updated to check for the flag.

In tex_layout_validate(), align the depth bo to 8x4 so that we can adjust
Width/Height of 3DSTATE_DEPTH_BUFFER without introducing out-of-bound access.

Finally in rectlist blitter, add the ability to adjust 3DSTATE_DEPTH_BUFFER.
ilo: handle NULL renderbuffers correctly

Renderbuffers may be NULL since 9baa45f78b8ca7d66280e36009b6a685055d7cd6.
i965: Enable native ETC texture support on Broadwell.

Broadwell, like Baytrail, has native ETC texture support.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
i965: Disable workaround flush for push constants on Broadwell.

If it wasn't necessary for Haswell, it's likely not to be necessary for
Broadwell either.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
i965: Emit 3DSTATE_VF on Broadwell too.

It's not just for Haswell.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>