remove obsolete pcie-axi-scratchpad
Update generate-constraints.py to allow other properties
*io_vita_clk_out_p is LVDS_25
*io_vita_clk_out_p is LVDS_25
added mkClockGenerator7Adv
remove manually created imageon .xdc files
added --tcl option to genxps to augment vivado synthesis/implementation script
added dependence gen: pregen to Makefile.common
remove some more unused clocks and resets in imageon example
use mkClockGenerator7Adv instead of mkMMCMHACK which left clkfbin pin disconnected
fixed syntax error in genxps
combine the XBSVFLAGS in examples/imageon/Makefile
ok, gen: pregen causes problems
but :: does the trick
wildcard for *miso_v pin
reducing overhead of new mem server implementation through extra type futzing
Pipelined RegFileA

Change-Id: I3cbb954c21293f405a4743578e052ab41232f381
added support for multi-beat reads to AxiMasterEngine
fixed compilation errors in testpci.cpp
moved PCIE CSR to bsv/AxiCsr.bsv