i965: Combine offset/texture_offset fields.

texture_offset was only used by some texturing operations, and offset
was only used by spill/unspill and some URB operations. These fields are
never used at the same time.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
i965: Move common fields into backend_instruction.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
i965/fs: Move ip_record class to its one use.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
i965/fs: Remove unused apply_stride().

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
i965/fs: Remove is_valid_3src() checks from emit_lrp.

The visitor emits MOVs to temporary registers for immediates, so these
never trigger. For further proof, check case ir_triop_fma.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
i965/fs: Remove is_valid_3src().

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
i965/vec4: Extract depctrl hazards

Move this to a separate function so that we can begin to add other little
caveats without making too big a mess.

NOTE: There is some desire to improve this function eventually, but we need to
fix a bug first.

v2:
Use const for the inst for the hazard check (Matt)
Invert safe logic to get rid of the double negative (Matt)
Add PRM reference for predicates (Matt)
Add note about empirical evidence for math (Matt)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965/vec4/gen8: Handle the MUL dest hazard exception

Fix one of the few cases where we can't reliable touch the destination hazard
bits. I am explicitly doing this patch individually so it is easy to backport. I
was tempted to do this patch before the previous patch which reorganized the
code, but I believe even doing that first, this is still easy to backport.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84212
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Make Gen4-5 push constants call _mesa_load_state_parameters too.

In commit 5e37a2a4a8a, I made the pull constant code stop calling
_mesa_load_state_parameters() when there were no pull parameters.

This worked fine on Gen6+ because the push constant code also called
it if there were any push constants.  However, the Gen4-5 push constant
code wasn't doing this.  This patch makes it do so, like the Gen6+ code.

A better long term solution would be to make core Mesa just handle this
for us when necessary.

Fixes around 8766 Piglit tests on Ironlake, and probably Gen4 as well.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: Mark Janes <mark.a.janes@intel.com>
Add release notes for the 10.3.4 release

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 26c8ecd85dade7be5759c4de0b3916fbc186dc43)
docs: Add sha256 sums for the 10.3.4 release

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 72c27d7a3acc40b8a77a277f7cd975fb8e60dca5)
docs: add news item and link release notes for mesa 10.3.4

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
draw: allow LLVM use on non-SSE2 X86 cpus

This patch remove workaround related to LLVM < 3.2 bug.

Original bug has been closed as fixed in 2011.
At this moment gallium requires LLVM 3.3 (2013).

LLVM has been tested without SSE2 support in commit
ca70de9bd20bc4a11b2d2d368e0cc1f49527a947 and removed after requiring
LLVM 3.3 in commit 013ff2fae13da41c2f5619c4698b0a7b5aa6a06d

Original LLVM bug: http://llvm.org/bugs/show_bug.cgi?id=6960

Signed-off-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
i915g: Don't hardcode array size for phase count

This is an array of temp registers, so use I915_MAX_TEMPORARY for the size.

Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
i915g: Don't write constants past I915_MAX_CONSTANT

This happens with glsl-convolution-1, where we have 64 constants. This
doesn't make the test pass (we don't have 64 constants anyway, only
32) but this prevents it from crashing.

Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
i915g: Fix offset for level != 0

For NPOT texture layouts, we want to be able to access texture levels
other than 0 directly. Since the hw doesn't support that, We do it by
adding the offset directly.

Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
i915g: Fix maxlod computation.

Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
i915g: Fix typos

Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
i915g: Align all texture dimensions to the next POT

This creates a usable layout for all NPOT textures. Of course these
still have lots of limitations, but at least we can render to a
level.

Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
i915g: Don't limit blitter to POT textures

Now that we have NPOT support for u_blitter, there is no reason to
limit this any longer.

Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>