Fix line endings before adding RUN lines, NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214320 91177308-0d34-0410-b5e6-96231b3b80d8
UseListOrder: Visit global values

When predicting use-list order, we visit functions in reverse order
followed by `GlobalValue`s and write out use-lists at the first
opportunity.  In the reader, this will translate to *after* the last use
has been added.

For this to work, we actually need to descend into `GlobalValue`s.
Added a targeted test in `use-list-order.ll` and `RUN` lines to the
newly passing tests in `test/Bitcode`.

There are two remaining failures in `test/Bitcode`:

  - blockaddress.ll: I haven't thought through how to model the way
    block addresses change the order of use-lists (or how to work around
    it).

  - metadata-2.ll: There's an old-style `@llvm.used` global array here
    that I suspect the .ll parser isn't upgrading properly.  When it
    round-trips through bitcode, the .bc reader *does* upgrade it, so
    the extra variable (`i8* null`) has an extra use, and the shuffle
    vector doesn't match.

    I think the fix is to upgrade old-style global arrays (or reject
    them?) in the .ll parser.

This is part of PR5680.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214321 91177308-0d34-0410-b5e6-96231b3b80d8
Retain alignment requirements for load->selects modified by DAGCombine

DAGCombine may choose to rewrite graphs where two loads feed a select into
graphs where a select of two addresses feed a load. While it sanity checks the
loads to make sure they are broadly equivalent it currently just uses the
alignment restriction of the left node. In cases where the right node has
stronger alignment requiresment this may lead to bad codegen, such as generating
an aligned load where an unaligned load is required. This patch makes the
combine generate a load with an alignment that is the same as whichever is more
restrictive of the two alignments.

Tests included.

rdar://17762530

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214322 91177308-0d34-0410-b5e6-96231b3b80d8
Fixing a few -Woverloaded-virtual warnings by exposing the hidden virtual function as well. No functional changes intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214325 91177308-0d34-0410-b5e6-96231b3b80d8
Refactor duplicated code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214328 91177308-0d34-0410-b5e6-96231b3b80d8
LangRef: add a note about the mangling-suppressing \01 prefix

Someone asked about this on IRC the other day, and I couldn't
find the magic prefix documented anywhere.

Differential Revision: http://reviews.llvm.org/D4728

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214329 91177308-0d34-0410-b5e6-96231b3b80d8
Fix test case introduced in r214322

This patch adds an explicit triple to the test case introduced by r214322. This
should fix build failueres that are occuring on bots that are cross building.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214330 91177308-0d34-0410-b5e6-96231b3b80d8
docs: update the command guide documentation for llvm-profdata.

Differential Revision: http://reviews.llvm.org/D4726


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214331 91177308-0d34-0410-b5e6-96231b3b80d8
Add BookE's tlbre, tlbwe and tlbivax instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214332 91177308-0d34-0410-b5e6-96231b3b80d8
SimplifyCFG: Avoid miscompilations due to removed lifetime intrinsics.

The lifetime intrinsics need some work in order to make it clear which
optimizations are or are not valid.

For now dropping this optimization avoids a miscompilation.

Patch by Björn Steinbrink.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214336 91177308-0d34-0410-b5e6-96231b3b80d8
SLP Vectorizer: Canonicalize tree operands of commutitive binary operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214338 91177308-0d34-0410-b5e6-96231b3b80d8
Add rfdi and rfmci from the e500/e500mc ISA.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214339 91177308-0d34-0410-b5e6-96231b3b80d8
InstCombine: Simplify (A ^ B) or/and (A ^ B ^ C)

While we can already transform A | (A ^ B) into A | B, things get bad
once we have (A ^ B) | (A ^ B ^ Cst) because reassociation will morph
this into (A ^ B) | ((A ^ Cst) ^ B).  Our existing patterns fail once
this happens.

To fix this, we add a new pattern which looks through the tree of xor
binary operators to see that, in fact, there exists a redundant xor
operation.

What follows bellow is a correctness proof of the transform using CVC3.

$ cat t.cvc
A, B, C : BITVECTOR(64);

QUERY BVXOR(A, B) | BVXOR(BVXOR(B, C), A) = BVXOR(A, B) | C;
QUERY BVXOR(BVXOR(A, C), B) | BVXOR(A, B) = BVXOR(A, B) | C;

QUERY BVXOR(A, B) & BVXOR(BVXOR(B, C), A) = BVXOR(A, B) & ~C;
QUERY BVXOR(BVXOR(A, C), B) & BVXOR(A, B) = BVXOR(A, B) & ~C;

$ cvc3 < t.cvc
Valid.
Valid.
Valid.
Valid.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214342 91177308-0d34-0410-b5e6-96231b3b80d8
[FastISel][AArch64] Add support for shift-immediate.

Currently the shift-immediate versions are not supported by tblgen and
hopefully this can be later removed, once the required support has been
added to tblgen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214345 91177308-0d34-0410-b5e6-96231b3b80d8
[FastISel][AArch64] Create helper functions to create the various multiplies on AArch64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214346 91177308-0d34-0410-b5e6-96231b3b80d8
[FastISel] Move the helper function isCommutativeIntrinsic into FastISel base class.

Move the helper function isCommutativeIntrinsic into the FastISel base class,
so it can be used by more than just one backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214347 91177308-0d34-0410-b5e6-96231b3b80d8
[FastISel][AArch64] Add {s|u}{add|sub|mul}.with.overflow intrinsic support.

This commit adds support for the {s|u}{add|sub|mul}.with.overflow intrinsics.
The unit tests for FastISel will be enabled in a later commit, once there is
also branch and select folding support.

This is related to <rdar://problem/17831117>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214348 91177308-0d34-0410-b5e6-96231b3b80d8
[FastISel][AArch64] Add branch folding support for the XALU intrinsics.

This improves the code generation for the XALU intrinsics when the
condition is feeding a branch instruction.

This is related to <rdar://problem/17831117>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214349 91177308-0d34-0410-b5e6-96231b3b80d8
[FastISel][AArch64] Add select folding support for the XALU intrinsics.

This improves the code generation for the XALU intrinsics when the
condition is feeding a select instruction.

This also updates and enables the XALU unit tests for FastISel.

This fixes <rdar://problem/17831117>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214350 91177308-0d34-0410-b5e6-96231b3b80d8
X86 asm parser: Use a loop to disambiguate suffixes instead of copy paste

This works towards making the Intel syntax asm matcher use a completely
different disambiguation strategy.

No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214352 91177308-0d34-0410-b5e6-96231b3b80d8