Removed misplaced 1
Removed misplaced 1
Design changes for BitRegister
A lot of renaming and basic structure - bit gate does not work yet
Activate and deactivate bit
BitRegister bit gate working
Reacting correctly to 0 on the gate controlling wires at memories.
Finished BitRegister to react correctly to bit and value changes depending on the state of gates.
Processing bitWire feedback correctly
Toggling wire gate by clicking on the arrows.
Refactored the model but forgot to change the call. This is callable now.
Wiring up BitRegisters completely. I forgot to enroll to the wires controlling the bit side.
Correct coloring for buses without specified color.
Real flank triggered input at BitRegister wideGate
Repaired view update logic.
Colored ones in BitRegister
Bitregister Gates throwing exceptions for simultaneous reads and writes.
Register gates throwing exceptions for simultaneous reads and writes.
Memory data bus gate throwing exceptions for simultaneous reads and writes.
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