fromNode improperly was using the cloned Nodes (which generally had no connections to other nodes) to get reference widths. This caused cloning of Nodes where the inference constraint was not fixWidth (e.g. cloning a type node for a Literal) to fail strangely. Fixed by having fromNode use the original structure (which will have proper connections) to get reference widths. Note, there are still substantial issues with calling getWidth on Aggregate types (generally non-sensical results) and circuitous behavior of getWidth (increasing debugging difficulties) that need to be addressed in future refactorings.
Merge branch 'master' into rearrange_passes
don't check assertions during reset in Verilog backend
add assertion check option
Adjust Aggregate (parent of Vec and Bundle) to intercept getWidth calls and actually calculate the projected width properly. Also, moved Aggregate into its own file so that it is easier to find. Note, the getWidth implementation for Aggregate is relatively simple (in that it merely calls getWidth on constituent elements and adds them together) and thus does not account for all the weird states a design could be in with respect to width inference.
Properly handle the issue of type erasure on a match in the SystemC backend code. Will throw an exception if the DecoupledIO is not of type Bits.
Merge pull request #252 from ucb-bar/fixassert

Fixes and enhancements to asserts
Preliminary code to compare generated files with simple substitutions.
Correct token splitting regex so it returns delimiters, allowing us to re-assemble the tokenized text with substitutions.
Cleanup warnings.
Merge pull request #255 from ucb-bar/assertfilesubstitute

Assertfilesubstitute
Merge branch 'master' into rearrange_passes

Conflicts:
	src/main/scala/Data.scala
Cleanup following merge with master.

setPseudoName() was removed from class Aggregate with donggyukim's
rearrange_passes branch. Ensure it stays removed.