Work on microcode up to last sw state (#2)
Split bits, styled MC (#2)
Corrected split on MC, will be hooked up on test branch (#2)
Added Dr-split circuit to propogate driversigs (#2)
Added Ld-split circuit to propgate Ld sigs (#2)
Complete microcode up to jalr0, corrected FSM, connect offset (#2)
Microcode complete, change FSM so halt stops via loop (#2)
Changes to chkZ logic in MC, compiled hex microcode (#2)
Add label to main ROM (#2)
Added labels for clarity, loaded microcode into ROMs (#2)
Begin wiring to microcontroller (#2)
More work on wiring (#2)
Everything's hooked up, time to debug! (Completes #2/Phase 2)