Sigh! Seagull is runnable from SRAM now

What I've learnt:

- BOOT0 low - flash
  BOOT0 high (VDD), BOOT1 low - system bootloader
  BOOT0 high (VDD), BOOT1 high (VDD) - SRAM

- Cortex-M4 maps 0x00000000-* region depending on the boot source. If
  its SRAM the region is mapped to 0x20000000-*

- `info reg pc' does not always correspond to `monitor reg pc', for
  other registerns too.

- After connecting to the JTAG the code must be uploaded by GDB command
  'load'.

- Reset does not invalidate SRAM

- All function symbols for ARMv7-M must have odd addresses because LSB
  of the PC, when written, defines the mode of the processor (bit T in
  EPSR). Since ARMv7-M works only in Thumb mode the bit must always be
  set. In assembly language it's done by ARM specific .thumb_func
  assembler directive. For C code it's done automatically. If the bit is
  not set when an instruction is called Hard Fault exception (vector 3)
  is generated.