Defer loadmanage first call until collected state is read.
Makes LB go faster

Only read the gateway once per lb phase
change step getway to step gateway.
Merge branch 'master' into PredictiveLoadBalance
Show the net gateway, don't let it get overrridden by the old SST.
.1 step... just for funsies.
Fix to run at FSU. FIXME
Reverting breaking changes caused by 1.53 usage.
Revert
load balance uses dgiEnable
Merge pull request #214 from scj7t4/RtdsInfo

load balance uses dgiEnable
Testing results for PLB

- Timings updated to have 15sec Load Balance across the board.
- Timings samples updated for LB_SC_QUERYTIME parameter which was missing in some.
- CRTDSAdapter has endian swap fix applied.
- Loadbalance.cpp has been updated to only operate when dgi-enable is set. This required the DGI to send commands to the RTDS while the RTDS has the dgi disabled, but the commands should only hold the current value. This was to prevent an issue where a 0 value would be read by the RTDS when the DGI was enabled, because no commands had been sent from the DGI to the RTDS.
Closes the connection if more than 3 messages are dropped.
Don't throw exception if hostname can't be resolved.
Update freedm.dxy

doxygen 1.8.5 is complaining about obsolete options in freedm.dxy.
They're obscure and probably unnecessary for older doxygen, so let's
update the whole thing as it suggests.
trivial: style changes in top-level CMakeLists.txt
Fix lots of whitespace errors

I unintelligently set my text editor to remove trailing whitespace from
the files I was editing. Now, in a side branch, I have a huge diff made
even worse by the whitespace changes. This helps reduce that.
trivial: code style in CBroker.cpp
Fix const-correctness issues in CClockSynchronizer
Merge branch 'trivial/ClockSynchronizerConst' into protobuf_noprotobufs

Conflicts:
	Broker/src/CClockSynchronizer.cpp
	Broker/src/CClockSynchronizer.hpp
trivial: code style in CClockSynchronizer.hpp