ARM: dts: zynq: Add SPI

Signed-off-by: Andreas Färber <afaerber@suse.de>
ARM: dts: zynq: Add QSPI for Parallella

Prepare SPI0 and SPI1 while at it.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Documentation: devicetree: Fix Xilinx VDMA specification

The specification requires xlnx,data-width, but example and driver use
xlnx,datawidth. Change the specification to match the implementation.

Signed-off-by: Andreas Färber <afaerber@suse.de>
ARM: dts: zynq: Add VDMA to Parallella

Signed-off-by: Andreas Färber <afaerber@suse.de>
Documentation: devicetree: Fix ADI AXI SPDIF specification

The specification requires compatible = "adi,axi-spdif-1.00.a" but
driver and example and file name indicate "adi,axi-spdif-tx-1.00.a".
Change the specification to match the implementation.

Signed-off-by: Andreas Färber <afaerber@suse.de>
ARM: dts: zynq: Add SPDIF for Parallella

Signed-off-by: Andreas Färber <afaerber@suse.de>
ARM: dts: zynq: Add AXI clkgen for Parallella

Signed-off-by: Andreas Färber <afaerber@suse.de>
usb: chipidea: zynq: Add device tree binding information

Document device tree binding information as required by
the ZYNQ USB controller.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
usb: chipidea: Add support for zynq usb host and device controller

Zynq soc uses Chipidea/Synopsys usb IP core(CI13612). This patch adds
necessary glue to allow the chipidea driver to work on zynq soc.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
TEST_ONLY: ARM: dts: zynq: Add USB to Parallella

Awaiting generic Chipidea driver and bindings, this wires up the
proposed v2 of a Zynq-specific driver.

Signed-off-by: Andreas Färber <afaerber@suse.de>
ARM: dts: parallella: Try adding flash

Signed-off-by: Andreas Färber <afaerber@suse.de>