Cosmetic change

moved a divider comment to right place
New scheme: no control logic required!
Adjusted increment and offset adders

Proper initialization for simulation using delay_line
Adjusted pipeline stages
Removed control signals, vectored offset and increment signals.
No more Block Counter to feed

Only one read (thread 0) and write (thread 4) signals.
Adjusted pipeline depth
Still in progress: top-level, memory-mapping, and actual addressing modules

Mostly, needs address decoders for indirect and shared hardware memory maps
(grep for "TODO")