hdl/*: (1/3) massive dsp changes

* Changed to a Time-division multiplexing approach.
	We are using a 2-multilplexed stream scheme for
	high frequencies (ADC rate) and a 4-multiplexed
	stream scheme for all the other lower rates.

* Oversampling rate of 2 relative to ADC rate.
	Now, a 2xADC rate clock is used for all the
	DSP chain. It allows for a reduced number of
	resources usage	at higher rates.

* Fix delta-sigma pre-divider FIFO buffers

* Add 25-bit multipliers for Kx, Ky and Ksum (position
measurement constants)

* Lower order of BPF at the beggining of the chain, in order
to reduce the number of FPGA resources used (mainly DSP48E1).
Also, we are using an oversample rate of 2, so, rougly, 2 times
less resources are used.

TODO:

* 4-channel DDS for independent frequency selection.
* Programmable DDS frequency for all channels.
* Programmable DDS phase offset for all channels.
* Reloadable filter coefficients.


Former-commit-id: 3cb5d6551a9097257deeabaab03957c01c285349
models/*: (2/3) massive dsp changes

* Changed to a Time-division multiplexing approach.
	We are using a 2-multilplexed stream scheme for
	high frequencies (ADC rate) and a 4-multiplexed
	stream scheme for all the other lower rates.

* Oversampling rate of 2 relative to ADC rate.
	Now, a 2xADC rate clock is used for all the
	DSP chain. It allows for a reduced number
	of resources usage at higher rates.

* Fix delta-sigma pre-divider FIFO buffers

* Add 25-bit multipliers for Kx, Ky and Ksum
	(position measurement constants)

* Lower order of BPF at the beggining of the chain,
	in order to reduce the number of FPGA resources
	used (mainly DSP48E1).Also, we are using an
	oversample rate of, so, rougly, 2 times
	less resources are used.

TODO:

* 4-channel DDS for independent frequency selection.
* Programmable DDS frequency for all channels.
* Programmable DDS phase offset for all channels.
* Reloadable filter coefficients.


Former-commit-id: b14340f114e3392e593ec099f9513cc8cd7a2fc7
scripts/*: (3/3) massive dsp changes

 * Changed to a Time-division multiplexing approach.
         We are using a 2-multilplexed stream scheme for
         high frequencies (ADC rate) and a 4-multiplexed
         stream scheme for all the other lower rates.

 * Oversampling rate of 2 relative to ADC rate.
         Now, a 2xADC rate clock is used for all the
          DSP chain. It allows for a reduced number
          of resources usage at higher rates.

  * Fix delta-sigma pre-divider FIFO buffers

  * Add 25-bit multipliers for Kx, Ky and Ksum
          (position measurement constants)

  * Lower order of BPF at the beggining of the chain,
         in order to reduce the number of FPGA resources
          used (mainly DSP48E1).Also, we are using an
          oversample rate of, so, rougly, 2 times
          less resources are used.

TODO:

* 4-channel DDS for independent frequency selection.
* Programmable DDS frequency for all channels.
* Programmable DDS phase offset for all channels.
* Reloadable filter coefficients.


Former-commit-id: 49794996a3fab6bbe43804d585ec64c908f15517
hdl/*: (1/2) Fix all last and ch_out signal delays

The main issue was due to CIC and FIR last signal. We must set
it to one cycle before the actual last TDM data (sysgen bug?)


Former-commit-id: 20fbf3921b989a980e2b56f7f96e4c2b523e66b5
models/*: (2/2) Fix all last and ch_out signal delays

The main issue was due to CIC and FIR last signal. We must set
it to one cycle before the actual last TDM data (sysgen bug?)


Former-commit-id: c272899ebeb383f6a78c0595d3c99cbec9c83ee4
hdl/*/ddc_bpm_476_066_cw.ucf: comment out overconstraints


Former-commit-id: 6a4ebc580504dd7dcdd6a3f59780f26e3ccce0f0
hdl/*: add xlclockdriver component to package


Former-commit-id: e1b26025e792bd2b16c4ef52ea24a3fea9799608
Merge branch 'devel'


Former-commit-id: 58790f5ab5d6de4f3bf0cba9e9644cb2f053472a
hdl/*/wb-un_cross/*: add initial switching dsp support


Former-commit-id: 62ed9ab8dce652c922bd1cb86298c86f704f25a0
hdl/*/wb_position_calc/*: integrate dsp chain with switching module


Former-commit-id: 1299e608eeb8991a0dddde7895fc5fd6bcd403ad
hdl/*/dsp_cores_pkg.vhd: move package and add new modules


Former-commit-id: 0365e069bb99b2be6cd13d327a770630ad3a76bc
hdl/*/Manifest.py: update various Manifests


Former-commit-id: 5e1098ca6f5906f39dee6815c41e02d893dd6a77
scripts/*: add missing scripts and cosmetic changes

cherry-pick commit from branch master


Former-commit-id: b3791e18768892daa915c4c33e9d745656696a02
hdl/*/wb_un_cross/*: remove package dependencies


Former-commit-id: b6b06882f96be67194a677279978cfe41794f14b
hdl/*/wb_un_cross/*: remove custom_wishbone package reference


Former-commit-id: e84bdd011abef7947398f595f1d2ca674ba9dffb
various: delete .orig and swap files

Former-commit-id: f128bdb72ac2cc4750a84001bdd533da86e2bb18
.gitignore: add .orig files


Former-commit-id: f537ef3129ba2c9b1e2b583bc079fff2e5868180
hdl/*/position_calc_core.ucf: more generic NET matching


Former-commit-id: 48ac72aea3c2f81f36203f83b4e94097d78ae2bc
hdl/*/wb_position_calc_core.vhd: fix wrong clock input


Former-commit-id: 6d699b76b9c4ab9a16481bbfb22bd10dd525db3a
Merge branch 'devel'


Former-commit-id: 7875f814d249bd23ada9ea0c20c2817aaac7cbc8