fame1 queue compiles
fix build.scala
remove fame1 instance variables from Module.scala; disable memory enables with fire signals
merge with master
update nameIt in FameBackend
new io transform
fix fame1 transform for sequential mems
use regular register enables for mem seq read ports in CPP backend
fix io issues with referencechip
Merge branch 'master' of github.com:ucb-bar/chisel into fame1-transform
add fpga backend
Merge branch 'master' of github.com:ucb-bar/chisel
remove backup files accidentally committed
update expected test results

Update expected test results to reflect Yunsup's commit: random numbers
with RANDOM_SEED 2b97ddf; compare reference and test Verilog files
after eliminating blank lines.
elaborate counter structure hierarhy / counter wrappers
modifies step function in an emulator header file so that testers work expectedly
Merge branch 'master' of https://github.com/ucb-bar/chisel into counter
merge