Rename argument strings of codegen passes to avoid collisions with command line
options.

This commit changes the command line arguments (PassInfo::PassArgument) of two
passes, MachineFunctionPrinter and MachineScheduler, to avoid collisions with
command line options that have the same argument strings.

This bug manifests when the PassList construct (defined in opt.cpp) is used
in a tool that links with codegen passes. To reproduce the bug, paste the
following lines into llc.cpp and run llc.

#include "llvm/IR/LegacyPassNameParser.h"
static llvm::cl::list<const llvm::PassInfo*, bool, llvm::PassNameParser>
PassList(llvm::cl::desc("Optimizations available:"));

rdar://problem/19212448


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224186 91177308-0d34-0410-b5e6-96231b3b80d8
Use range-based for loops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224187 91177308-0d34-0410-b5e6-96231b3b80d8
Silencing a *lot* of -Wsign-compare warnings; NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224194 91177308-0d34-0410-b5e6-96231b3b80d8
Silencing a -Wsign-compare warning; NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224195 91177308-0d34-0410-b5e6-96231b3b80d8
Fix Doxygen command misspellings.

Found by -Wdocumentation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224197 91177308-0d34-0410-b5e6-96231b3b80d8
Revert "[ARM] Combine base-updating/post-incrementing vector load/stores."

This reverts commit r223862, as it created a regression on the test-suite
on test MultiSource/Benchmarks/Ptrdist/anagram by scrambling the order
in which the words are shown. We'll investigate the issue and re-apply
when safe.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224198 91177308-0d34-0410-b5e6-96231b3b80d8
Reapply "[ARM] Combine base-updating/post-incrementing vector load/stores."

r223862 tried to also combine base-updating load/stores.
r224198 reverted it, as "it created a regression on the test-suite
on test MultiSource/Benchmarks/Ptrdist/anagram by scrambling the order
in which the words are shown."
Reapply, with a fix to ignore non-normal load/stores.
Truncstores are handled elsewhere (you can actually write a pattern for
those, whereas for postinc loads you can't, since they return two values),
but it should be possible to also combine extloads base updates, by checking
that the memory (rather than result) type is of the same size as the addend.

Original commit message:
We used to only combine intrinsics, and turn them into VLD1_UPD/VST1_UPD
when the base pointer is incremented after the load/store.

We can do the same thing for generic load/stores.

Note that we can only combine the first load/store+adds pair in
a sequence (as might be generated for a v16f32 load for instance),
because other combines turn the base pointer addition chain (each
computing the address of the next load, from the address of the last
load) into independent additions (common base pointer + this load's
offset).

Differential Revision: http://reviews.llvm.org/D6585


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[PowerPC] Handle cmp op promotion for SELECT[_CC] nodes in PPCTL::DAGCombineExtBoolTrunc

PPCTargetLowering::DAGCombineExtBoolTrunc contains logic to remove unwanted
truncations and extensions when dealing with nodes of the form:
  zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)

There was a FIXME in the implementation (now removed) regarding the fact that
the function would abort the transformations if any of the non-output operands
of a SELECT or SELECT_CC node would need to be promoted (because they were
also output operands, for example). As a result, we continued to generate
unnecessary zero-extends for code such as this:

  unsigned foo(unsigned a, unsigned b) {
    return  (a <= b) ? a : b;
  }

which would produce:

  cmplw 0, 3, 4
  isel 3, 4, 3, 1
  rldicl 3, 3, 0, 32
  blr

and now we produce:

  cmplw 0, 3, 4
  isel 3, 4, 3, 1
  blr

which is better in the obvious way.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224213 91177308-0d34-0410-b5e6-96231b3b80d8
ScalarEvolution: Remove SCEVUDivision, it's unused

This is just a code simplification, no functionality change is intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224216 91177308-0d34-0410-b5e6-96231b3b80d8
APInt: udivrem should use machine instructions for single-word APInts

This mirrors the behavior of APInt::udiv and APInt::urem.  Some
architectures, like X86, have a single instruction which can compute
both division and remainder.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224217 91177308-0d34-0410-b5e6-96231b3b80d8
Loop Vectorizer minor changes in the code - 
some comments, function names, identation.

Reviewed here: http://reviews.llvm.org/D6527


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224218 91177308-0d34-0410-b5e6-96231b3b80d8
Use unique_ptr to remove explicit delete.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224224 91177308-0d34-0410-b5e6-96231b3b80d8
ThreadLocal: Return a mutable pointer if templated with a non-const type

It makes more sense for ThreadLocal<const T>::get to return a const T*
and ThreadLocal<T>::get to return a T*.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224225 91177308-0d34-0410-b5e6-96231b3b80d8
StringPool: Cleanup typos in unittest comments

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224226 91177308-0d34-0410-b5e6-96231b3b80d8
ThreadLocal: Move Unix-specific code out of Support/ThreadLocal.cpp

Just a cleanup, no functionality change is intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224227 91177308-0d34-0410-b5e6-96231b3b80d8
Fix line mapping information in LLVM JIT profiling with Vtune
The line mapping information for dynamic code is reported incorrectly. It causes VTune to map LLVM generated code to source lines incorrectly. This patch fix this issue.
Patch by Denis Pravdin.
Differential Revision: http://reviews.llvm.org/D6603


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224229 91177308-0d34-0410-b5e6-96231b3b80d8
AVX-512: Added EXPAND instructions and intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224241 91177308-0d34-0410-b5e6-96231b3b80d8
Typo Correction in Test Case. NFC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224244 91177308-0d34-0410-b5e6-96231b3b80d8
[X86] Break false dependencies before partial register updates when the source operand is in memory

Adds the various "rm" instruction variants into the list of instructions that have a partial register update. Also adds all variants of SQRTSD that were missing in the original list.

Differential Revision: http://reviews.llvm.org/D6620

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224246 91177308-0d34-0410-b5e6-96231b3b80d8
Sink store based on alias analysis
 - by Ella Bolshinsky
The alias analysis is used define whether the given instruction
is a barrier for store sinking. For 2 identical stores, following
instructions are checked in the both basic blocks, to determine
whether they are sinking barriers.

http://reviews.llvm.org/D6420



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224247 91177308-0d34-0410-b5e6-96231b3b80d8