ARM: tegra20: pm: flush L1 data before exit coherency

Bug 934368

Change-Id: I960d8ae5c6390e719b8ee6c9cbc067cf8d28122d
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/92543
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
ARM: tegra: fiq_debugger: restore FCR to correct value on resume

Make sure we get an interrupt on every character in RX FIFIO.
There's a syscore debug uart resume that forces the triggers too high.
This may work for DEBUG_LL, but for interactive console we need RX
trigger to be 1 char.

Change-Id: Icd83e30807b59dade7093d68286fa2dd92a640ce
Signed-off-by: Dima Zavin <dima@android.com>
ARM: tegra: fiq_debugger: enable uart fifo

Change-Id: I56bdf6d7a53e3b9d28d62ccd85c403aa8b72ab65
Signed-off-by: Dima Zavin <dima@android.com>