Initial example commit. Added extensive .gitignore that filters out ISE intermediates.
Base proposal documents.
Added a lot to the proposal.
Add spi-master-slave OpenCore
SPI works now.
determ_adc now has a counter. This will be used to reset the signal after a certain time delay.
determ_adc now has state. Predictable signal still to come
Fixed a few small signal bugs. Still has a bug where if the state is > 0x10, MISO remains high.
updated the overview, theory and FPGA consideration sections. Theory may need a little more work
adding updated .pdf
Merge pull request #1 from gmassman/changes

Changes
Final changes to proposal.
Cleaned up code
Works in simulation, not synthesizable.
Synthesizes, but the output was changed. Probably doesn't work.
Now lines up with documentation diagram, synthesizes.
Fixed a longstanding bug where the first word was invalid.
Fixed another issue
Testing with toggling ssel. Seems to work.
Reverted previous changes.