[include][sys] add shorthand integer types

u8/u16/u32/u64 and s8/s16/s32/s64 for those who prefer minimum verbosity
[platform][zynq] initial fpga control routines

- zynq_program_fpga(physaddr,len) -- load bitstream
- zynq_reset_fpga() -- reset fpga
[lib][devicetree] first pass at library for dealing with devicetree

Basic validation and walking of flattened devicetree blobs.
[platform][zynq] initial implementation of some clock routines

-Mostly introspection at this point
-Move target specific jam table to early platform init
[platform][zynq] update clock routines to lock/unlock
[platform][zynq] during init, write to mandatory reserved register
[target][zynq-qemu] get the qemu target working after clock changes

The qemu target seems to emulate a 33Mhz crystal with default
pll settings.
[platform][zynq] fix uart driver
[platform][zynq] initialize more of the uart

no longer relies on the target specific jam table except for
baud rate calculations.
[platform][zynq] update clock setting api, print boot reason
[scripts] add script to build and zybo project via xmd
[dev][cache] initial implementation of PL310 cache controller

-Hook into the arm cache flush routines
[platform][zynq] enable PL310 L2 cache controller
[app][tests] add quick n' dirty cache test routine
[kernel][spinlock] move spinlocks into generic implementation in kernel

Kernel header provies framework for the arch to implement spinlocks.
At the moment, only arm implements it.
[app][tests] add quick spinlock test
WIP first stab at converting everything to spinlocks
WIP smp - actually boot arm secondary cpus