monster: fix indentation
monster: shift the correct (butis) clock
monster: add some debug output signals people can use for convenience
vme: include MSI-enabled VME
monster: include vme msi interface
monster:add pin to VME_Buffer_ctrl component
vetar: top design for testing msi irq
vme_wb: update the submodule
scu_slave: 	added two new input ports for the CID numbers of extension cards
		added new register for clk readout
		improved address decoding
Merge branch 'proposed_master' of https://github.com/stefanrauch/bel_projects into proposed_master
monster:add to vme module generics and a missing pin
monster: the butis global region module is commented out
in order to permit this clock to be assigned to
a Dedicated External Clock Output pin in the Vetar design
vme: update submodule
vetar:migration to monster top
Merge branch 'proposed_master' of github.com:stefanrauch/bel_projects into proposed_master
scu_diob: updated qsf
Merge branch 'proposed_master' into rolf-wip