R600: Move trivial getters into header, use initializer list

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211917 91177308-0d34-0410-b5e6-96231b3b80d8
lldb can interrupt waitpid, so EINTR shouldn't be an error. This fixes the case
where there is no timeout. In the case where there is a timeout though, the
code is still wrong since it doesn't check that the alarm really went off.

Without this patch, I cannot debug a program that forks itself using
sys::ExecuteAndWait with lldb.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211918 91177308-0d34-0410-b5e6-96231b3b80d8
cmake: Don't do anything for LLVM_ENABLE_ASSERTIONS=OFF

By default, CMake will set NDEBUG in Rel* builds and leave it off in
debug builds, so we shouldn't need to do anything ourselves.

Before this change, it was possible to a Debug build without assertions
(aka Debug-Asserts in the autoconf system) by configuring with
-DLLVM_ENABLE_ASSERTIONS=OFF, but this configuration isn't very useful.
You can still get the same effect by explicitly adding -DNDEBUG to
CFLAGS.

Differential Revision: http://reviews.llvm.org/D4257

Patch by Janusz Sobczak!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211919 91177308-0d34-0410-b5e6-96231b3b80d8
IR: Add COMDATs to the IR

This new IR facility allows us to represent the object-file semantic of
a COMDAT group.

COMDATs allow us to tie together sections and make the inclusion of one
dependent on another. This is required to implement features like MS
ABI VFTables and optimizing away certain kinds of initialization in C++.

This functionality is only representable in COFF and ELF, Mach-O has no
similar mechanism.

Differential Revision: http://reviews.llvm.org/D4178

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211920 91177308-0d34-0410-b5e6-96231b3b80d8
[x86] Fix a miscompile in the new shuffle lowering uncovered by
a bootstrap.

I managed to mis-remember how PACKUS worked on x86, and was using undef
for the high bytes instead of zero. The fix is fairly obvious.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211922 91177308-0d34-0410-b5e6-96231b3b80d8
Silencing some -Wcast-qual warnings. No functional changes intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211923 91177308-0d34-0410-b5e6-96231b3b80d8
Vectorization documentation for loop hint pragmas and Rpass diagnostics.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211924 91177308-0d34-0410-b5e6-96231b3b80d8
[NVPTX] Just use getTypeAllocSize() when computing return value size for structures and vectors

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211925 91177308-0d34-0410-b5e6-96231b3b80d8
[NVPTX] Emit .weak when linkage is not external, internal, or private

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211926 91177308-0d34-0410-b5e6-96231b3b80d8
[NVPTX] Directly control the Machine SSA passes that are invoked for NVPTX.

NVPTX is a bit special in the optimizations it requires, so this gives
us better control over the backend optimization pipeline.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211927 91177308-0d34-0410-b5e6-96231b3b80d8
[NVPTX] Update sub-target feature detection

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211928 91177308-0d34-0410-b5e6-96231b3b80d8
[NVPTX] Add target options for PTX 3.2/4.0 and SM 5.0 (Maxwell)

Default PTX version is set to PTX 3.2

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211929 91177308-0d34-0410-b5e6-96231b3b80d8
[NVPTX] Add support for envreg reads

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211930 91177308-0d34-0410-b5e6-96231b3b80d8
[NVPTX] Add support for isspacep instruction

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211931 91177308-0d34-0410-b5e6-96231b3b80d8
[NVPTX] Add isel patterns for bit-field extract (bfe)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211932 91177308-0d34-0410-b5e6-96231b3b80d8
[NVPTX] Add missing isel patterns for 64-bit atomics

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211933 91177308-0d34-0410-b5e6-96231b3b80d8
[NVPTX] Add support for efficient rotate instructions on SM 3.2+

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211934 91177308-0d34-0410-b5e6-96231b3b80d8
[NVPTX] Implement fma and imad contraction as target DAGCombiner patterns

This also introduces DAGCombiner patterns for mul.wide to multiply two smaller integers and produce a larger integer

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211935 91177308-0d34-0410-b5e6-96231b3b80d8
[NVPTX] Add support for [SHL,SRA,SRL]_PARTS

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211936 91177308-0d34-0410-b5e6-96231b3b80d8
[NVPTX] Add missing boolean vector contents flag

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211937 91177308-0d34-0410-b5e6-96231b3b80d8