ARM: cpu hotplug: remove majority of cache flushing from platforms

Remove the majority of cache flushing calls from the individual platform
files.  This is now handled by the core code.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>

Conflicts:
	arch/arm/mach-msm/hotplug.c
	arch/arm/mach-omap2/omap-hotplug.c

Change-Id: I77424117ca771e265df0ac8b7a9c18b6f5fa6ee7
ARM: 7645/1: ioremap: introduce an infrastructure for static mapped area

In current implementation, we used ARM-specific flag, that is,
VM_ARM_STATIC_MAPPING, for distinguishing ARM specific static mapped area.
The purpose of static mapped area is to re-use static mapped area when
entire physical address range of the ioremap request can be covered
by this area.

This implementation causes needless overhead for some cases.
For example, assume that there is only one static mapped area and
vmlist has 300 areas. Every time we call ioremap, we check 300 areas for
deciding whether it is matched or not. Moreover, even if there is
no static mapped area and vmlist has 300 areas, every time we call
ioremap, we check 300 areas in now.

If we construct a extra list for static mapped area, we can eliminate
above mentioned overhead.
With a extra list, if there is one static mapped area,
we just check only one area and proceed next operation quickly.

In fact, it is not a critical problem, because ioremap is not frequently
used. But reducing overhead is better idea.

Another reason for doing this work is for removing architecture dependency
on vmalloc layer. I think that vmlist and vmlist_lock is internal data
structure for vmalloc layer. Some codes for debugging and stat inevitably
use vmlist and vmlist_lock. But it is preferable that they are used
as least as possible in outside of vmalloc.c

Now, I introduce an ARM-specific infrastructure for static mapped area. In
the following patch, we will use this and resolve above mentioned problem.

Reviewed-by: Nicolas Pitre <nico@linaro.org>
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Joonsoo Kim <iamjoonsoo.kim@lge.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
ARM: 7542/1: mm: fix cache LoUIS API for xscale and feroceon

Some architectures like xscale and feroceon have cache API variants that
map cache flushing functions as aliases to the base architecture.
This patch adds the required aliases to complete the implementation of
cache flushing LoUIS API.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
ARM: 7680/1: Detect support for SDIV/UDIV from ISAR0 register

The ISAR0 register indicates support for the SDIV and UDIV
instructions in both the Thumb and ARM instruction set. Read the
register to detect the supported instructions and update the
elf_hwcap mask as appropriate. This is better than adding more
and more cpuid checks in proc-v7.S for each new cpu variant that
supports these instructions.

Acked-by: Will Deacon <will.deacon@arm.com>
Cc: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
ARM: 7587/1: implement optimized percpu variable access

Use the previously unused TPIDRPRW register to store percpu offsets.
TPIDRPRW is only accessible in PL1, so it can only be used in the kernel.

This replaces 2 loads with a mrc instruction for each percpu variable
access. With hackbench, the performance improvement is 1.4% on Cortex-A9
(highbank). Taking an average of 30 runs of "hackbench -l 1000" yields:

Before: 6.2191
After: 6.1348

Will Deacon reported similar delta on v6 with 11MPCore.

The asm "memory clobber" are needed here to ensure the percpu offset
gets reloaded. Testing by Will found that this would not happen in
__schedule() which is a bit of a special case as preemption is disabled
but the execution can move cores.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
ARM: rwsem: use asm-generic rwsem implementation

asm-generic offers an atomic-add based rwsem implementation, which
can avoid the need for heavier, spinlock-based synchronisation on the
fast path.

This patch makes use of the optimised implementation for ARM CPUs.

Change-Id: If5e211b3ac22ecc0e6e48860fcda8e38b25790e5
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
asm-generic: rwsem: ensure sem->cnt is only accessed via atomic_long_*

The asm-generic rwsem implementation directly acceses sem->cnt when
performing a __down_read_trylock operation. Whilst this is probably safe
on all architectures, we should stick to the atomic_long_* API and use
atomic_long_read instead.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
asm-generic: rwsem: de-PPCify rwsem.h

asm-generic/rwsem.h used to live under arch/powerpc. During its
liberation to common code, a few references to its former home where
preserved, in particular the definition of RWSEM_ACTIVE_MASK is
predicated on CONFIG_PPC64.

This patch updates the ifdefs and comments to architecturally neutral
versions.

Change-Id: I5a2ff562ac5373a0853ac8be8f311c40fd0c5dac
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
ARM: 7747/1: pcpu: ensure __my_cpu_offset cannot be re-ordered across barrier()

__my_cpu_offset is non-volatile, since we want its value to be cached
when we access several per-cpu variables in a row with preemption
disabled. This means that we rely on preempt_{en,dis}able to hazard
with the operation via the barrier() macro, so that we can't end up
migrating CPUs without reloading the per-cpu offset.

Unfortunately, GCC doesn't treat a "memory" clobber on a non-volatile
asm block as a side-effect, and will happily re-order it before other
memory clobbers (including those in prempt_disable()) and cache the
value. This has been observed to break the cmpxchg logic in the slub
allocator, leading to livelock in kmem_cache_alloc in mainline kernels.

This patch adds a dummy memory input operand to __my_cpu_offset,
forcing it to be ordered with respect to the barrier() macro.

Cc: <stable@vger.kernel.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
ARM: 7678/1: Work around faulty ISAR0 register in some Krait CPUs

Some early versions of the Krait CPU design incorrectly indicate
that they only support the UDIV and SDIV instructions in Thumb
mode when they actually support them in ARM and Thumb mode. It
seems that these CPUs follow the DDI0406B ARM ARM which has two
possible values for the divide instructions field, instead of the
DDI0406C document which has three possible values.

Work around this problem by checking the MIDR against Krait CPUs
with this faulty ISAR0 register and force the hwcaps to indicate
support in both modes.

[sboyd: Rewrote commit text to reflect real reasoning now that
	we autodetect udiv/sdiv]

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
ARM: 7408/1: cacheflush: return error to userspace when flushing syscall fails

The cacheflush syscall can fail for two reasons:

(1) The arguments are invalid (nonsensical address range or no VMA)

(2) The region generates a translation fault on a VIPT or PIPT cache

This patch allows do_cache_op to return an error code to userspace in
the case of the above. The various coherent_user_range implementations
are modified to return 0 in the case of VIVT caches or -EFAULT in the
case of an abort on v6/v7 cores.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>

Conflicts:
	arch/arm/mm/cache-v7.S

Change-Id: Ifce5399043c85ac5f27b3268a51c38d111bd8b0c
cpaccess: remove use of set_get_l2_indirect_reg()

cpaccess is the only client of set_get_l2_indirect_reg(), a special-
purpose API for writing an indirect Krait CP15 register and reading
back the new value. For simplicity, this API is being removed and
replaced with bacl-to-back calls to set_l2_indirect_reg() and
get_l2_indirect_reg(), which should perform comparably.

Change-Id: I868ae115265c59e58ffd37dc405a91c6962e0c3d
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
msm: krait-l2-accessors: Remove set_get_l2_indirect_reg() API

There are no remaining users of this API, which writes to an indirect
register and reads back the new value. To simplify the future addition
of RTB logging for L2 indirect CP15 accesses, remove the unused API.

set_l2_indirect_reg() and get_l2_indirect_reg() can be individually
called to accomplish the same purpose that set_get_l2_indirect_reg()
served, with a negligible performance difference for common usecases.

Change-Id: If372370eabda7cf5d9eee488222a17e139609a36
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
msm: krait-regulator: handle efuse differences

Scaling factor version is valid for
- 8974 based devices when the version bits read 1
- 8974pro based devices when the version bits read 1 or 2
- 8084 based devices when the version bits read 0
- 8092 based devices when the version bits read 0

Moreover the three bit scaling factor data for
- 8974 based devices starts at bit 16
- 8974pro based devices starts at bit 16
- 8084 based devices starts at bit 14
- 8092 based devices starts at bit 14

Update the code to handle these differences.

CRs-Fixed: 614657
Change-Id: I30c65026341ece9a03f88514127b563417df46ee
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>

Conflicts:
	arch/arm/mach-msm/krait-regulator.c
msm: krait-regulator: fix unnecessary calls to switch to LDO

When asked to set a LDO voltage the driver rounds it up to
the nearest step value. However, when checking if the requested voltage
is already set it doesn't account for the rounding up.

Fix this by rounding up the requested value, which avoids
unnecessary calls to set the LDO voltage and switch to LDO.

CRs-Fixed: 609879
Change-Id: Ia5a201721e39eece49dea3f61fbc585f116d5060
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
ARM: dts: Modify BKE limiting for Krait master

Modify the BKE limiting properties for Krait master by setting up 2
levels of threshold checks and limiting bandwidth values to be applied.
These levels of throttling are needed in certain concurrency usecases to
protect real time masters from surges in bus usage from some APSS masters.

Change-Id: I04d086e10df27d0f7cc1a234fe9eb36a9ea73e65
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
msm: krait-regulator-pmic: account for PWM_CL register security

The PWM_CL register is secure i.e. driver has to write 0xA5 to 0XD0
register to allow updates to PWM_CL register.

Fix it.

Change-Id: I3f273627bdc137d8c10768c7d5824abe96ee8707
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>