i965: Create a helper function for emitting PIPE_CONTROL flushes.

These days, we need to emit PIPE_CONTROL flushes all over the place.
Being able to do that via a single function call seems convenient.

Broadwell will also increase the length of these packets by 1; with the
refactoring, we should have to do this in substantially fewer places.

v2: Add back forgotten intel_emit_post_sync_nonzero_flush (caught by
    Eric Anholt).  Drop unlikely() from BLT_RING check.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
i965: Emit full-length PIPE_CONTROLs for (non-write) flushes.

The PIPE_CONTROL packet actually has 5 DWords on Gen6+:
1. Header
2. Flags
3. Address
4. Immediate Data: Lower DWord
5. Immediate Data: Upper DWord

We just never emitted the last one.  While it appears to work, it's
probably safer to emit the entire thing.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Use full-length PIPE_CONTROL packets for workaround writes.

I believe that PIPE_CONTROL uses the length field to decide whether to
do 32-bit or 64-bit writes.  A length of 4 would do a 32-bit write,
while a length of 5 would do a 64-bit write.  (I haven't verified this,
though.)

For workaround writes, we don't care what value gets written, or how
much data.  We're only writing something because hardware bugs mandate
that do so.  So using a 64-bit write should be fine.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Create a helper function for emitting PIPE_CONTROL writes.

There are a lot of places that use PIPE_CONTROL to write a value to a
buffer (either an immediate write, TIMESTAMP, or PS_DEPTH_COUNT).
Creating a single function to do this seems convenient.

As part of this refactor, we now set the PPGTT/GTT selection bit
correctly on Gen7+.  Previously, we set bit 2 of DW2 on all platforms.
This is correct for Sandybridge, but actually part of the address on
Ivybridge and later!

Broadwell will also increase the length of these packets by 1; with the
refactoring, we should have to adjust that in substantially fewer
places, giving us confidence that we've hit them all.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Re-combine the Gen4-5 and Gen6+ write_depth_count functions.

Now that we have a helper function that handles the PIPE_CONTROL
variations between the various platforms, these are basically the same.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Update PIPE_CONTROL packet lengths for Broadwell.

On Broadwell, PIPE_CONTROL needs an extra DWord to accomodate the
48-bit addressing.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Update blitter code for 48-bit addresses.

v2: Rebase on Eric's SET_FIELD changes.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v1]
i965: Reserve space for "Vertex Count" in GS outputs.

v2: Also increment ir->offset in the GS visitor, rather than at the
    final assembly generation stage (requested by Paul).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
draw: fix points with negative w coords for d3d style point clipping

Even with depth clipping disabled, vertices which have negative w coords
must be discarded. And since we don't have a proper guardband implementation
yet (relying on driver to handle all values except infs/nans in rasterization
for such points) we need to kill them off manually (as they can end up with
coordinates inside viewport otherwise).

v2: use 0.0f instead of 0 (spotted by Brian).

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
i965: Add GS support to INTEL_DEBUG=shader_time.

Previously, time spent in geometry shaders would be counted as part of
the vertex shader time.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Modify some error messages to refer to "vec4" instead of "vs".

These messages are in code that is shared between the VS and GS
back-ends, so use the terminology "vec4" to avoid confusion.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
mesa: add missing TYPE_DOUBLEN_2 cases in get.c

The new TYPE_DOUBLEN_2 type was added in 0e60d850 but the code to
return values of that type wasn't completed.

Fixes conform's default state test.  glGetFloatv(GL_DEPTH_RANGE)
wasn't returning anything.

v2: remove stray 'break' statements.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
svga: fix clearing for null color buffers

Fixes piglit "fbo-drawbuffers-none glClear" test.

Reviewed-by: José Fonseca <jfonseca@vmware.com>
svga: rename color output variables

Just to be bit more readable.

Reviewed-by: José Fonseca <jfonseca@vmware.com>
svga: implement TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS

Fixes several colorbuffer tests, including piglit "fbo-drawbuffers-none"
for "gl_FragColor" and "glDrawPixels" cases.

v2: rework patch to only avoid creating extra shader variants when
TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS is not specified.  Per Jose.
Use a write_color0_to_n_cbufs key field to replicate color0 to N
color buffers only when N > 0 and WRITES_ALL_CBUFS is set.

Reviewed-by: José Fonseca <jfonseca@vmware.com>
docs: remove some ancient README.* files

None of this info is relevant anymore.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
glsl: Extract function for record comparisons.

Reviewed-by: Matt Turner <mattst88@gmail.com>
glsl: Match unnamed record types across stages.

Unnamed record types are assigned to separate types per stage, e.g. if

uniform struct { ... } a;

is defined in both vertex and fragment shader, two separate types will
result with different names. When linking the shader, this results in a
type conflict. However, there is no reason why this should not be
allowed according to GLSL specifications. Compare and match record types
when linking shader stages to avoid this conflict.

Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Print reg_offset for vgrf of size > 1 in dump_instruction().

Previously we wouldn't print the +0 for the first part of a VGRF of size
greater than 1.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
i965/fs: Fix the example about overwriting uniforms in SIMD16.

mov takes only a single source argument. Example instruction
inexplicably changed from add to mov in commit f10f5e49.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>