WIP: target-xtensa: add GPIO32 coprocessor

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
hw/xtensa: add support for ML605 and KC705 FPGA board

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
opencores_eth: flush queue whenever can_receive can go from false to true

The following registers control whether MAC can receive frames:
- MODER.RXEN bit that enables/disables receiver;
- TX_BD_NUM register that specifies number of RX descriptors.
Notify QEMU networking core when the MAC is ready to receive frames.
Discard frame and raise BUSY interrupt when the frame arrives but the
current RX descriptor is not empty.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
target-xtensa: add RRRI4 opcode format fields

This encoding is used by cache instructions.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
target-xtensa: add basic checks to dcache opcodes

Check privilege level for privileged instructions (DHI, DHU, DII, DIU, DIWB,
DIWBI, DPFL are privileged), memory accessibility for instructions that
reference memory (all DH* and DPFL) and windowed register validity for all
data cache instructions.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
target-xtensa: add basic checks to icache opcodes

Check privilege level for privileged instructions (IHU, III, IIU and IPFL
are privileged), memory accessibility for instructions that reference memory
(IH* and IPFL) and windowed register validity for all instruction cache
instructions.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
target-xtensa: add overridable test_init macro

Some test suites, like MMU, need per-test initialization. Don't make them
redefine test macro, add test_init for that purpose.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
target-xtensa: allow using core configuration in tests

Add path to the core configuration directory to test build command and
replace .include asm directive with #include to enable preprocessing.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
target-xtensa: add basic tests for cache opcodes

Test that non-locking prefetch operations don't cause exceptions on
missing TLB and that other 'hit' cache operations do.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
target-xtensa: implement do_unassigned_access callback

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
WIP: target-xtensa: add definition for XTHAL_INTTYPE_PROFILING

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
target-xtensa: add test_kc705_ca core

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>