i965/compaction: Simplify jump target code.

My attempts to clarify the code with _compacted/_uncompacted prefixed
variables apparently failed. Hopefully this is clearer.

In any case, the previous code wasn't clear enough to gcc to let it
optimize division by a power of two into a shift. No problems now.

Also, the previous code (in the ADD case) didn't work on 32-bit x86, due
to complicated set of interactions best summed up as unsigned division
and compiler optimizations.

Tested-by: Mark Janes <mark.a.janes@intel.com>
i965/compaction: Move variable declarations to their uses.

Tested-by: Mark Janes <mark.a.janes@intel.com>
i965: Use BRW_MATH_DATA_SCALAR when source regioning is scalar.

Notice the mistaken (but harmless) argument swapping in brw_math_invert().

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
freedreno/ir3: add IDIV/UDIV support

Logic shamelessly copied from nv50 lowering pass.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
freedreno/ir3: add UMOD support, based on UDIV

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
freedreno/ir3: add ISSG support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
freedreno/ir3: add POPC/BREV/MSB/LSB opcode support

These are part of GLES3.1 and ARB_gpu_shader5. The bitfield
extract/insert operations are still to be done.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
freedreno/ir3: make TXQ return integers, not floats

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
freedreno/ir3: add TXF support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
freedreno/ir3: add texture offset support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
freedreno/ir3: add TXD support and expose ARB_shader_texture_lod

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
freedreno/ir3: add TG4 support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
fix offsets
fix txd
add.s neg -> sub.s, etc