[FIX] Add missing definitions for xilinx platform in global.h

* Split _DEV_MICROBLAZE_ into big and little endian

Change-Id: I0495958eb08f9d344feb852e5ccd3832da170ea0
[TASK] Add trace macros for PDO module

Change-Id: I15526e7663242ebaf2102ec863d79972f8fe53b2
[TASK] Add bit-sized integer type macros

Change-Id: Ia08741225e7544475a37f8b5d343ba6b6d605124
[TASK] Implement macro UNUSED_PARAMETER()

The macro is implemented as a cast to void. This should
work for all used compilers.

Change-Id: I74f99120c858dcf97c72f2ec01eab3996f0fff83
[FIX] Replace "winpcap" by "pcap library" in the CN console demo

Change-Id: I0a29c6f70d517bc1cd13ebffdde25d2dbc179fc6
[TASK] update Altera POWERLINK IP-Core to V0.2.7

* fix bug if PDI DPR is larger 2 kB
* enhance DMA master path to 32 bit address width

Change-Id: I928a3df781253579808be83e56c2e9d6055aac19
[TASK] update Xilinx POWERLINK IP-Core to V0.2.7

* fix bug if PDI DPR is larger 2 kB
* fix BRAM size to values of power 2
* enhance DMA master path to 32 bit address width

Change-Id: Icb68f95a470511501b6b2079e18923bdf4fe5f4a
[TASK] update openMAC drivers to V0.2.7

* fix memory leak in omethlib
* fix sync-interrupt generation
* prepared for filling internal memory with functions


Change-Id: I5880dd28810e2b55b45d8d06a644cc42c670bcc1
[FEATURE] Move functions from interrupt context to internal memory

* Introduce internal memory map categories for altera and xilinx and different
  optimization levels -> needs opt level makros during compile time!
* Move time critical functions to internal memory.
* Reduce optimization level to -O2 (needs less TCM with the same performance)

Change-Id: I9b7d42c7c3d0a2a7217f1b1bec8e3cbd2d5a5f14
[TASK] update Altera directIO examples

The examples are recompiled with POWERLINK IP-Core V0.2.7.

note: SYSTEC_ECUcore-EP3C untested!

Change-Id: I6eda6631968f7c8a1e512e41f283f42bed43c8c1
[TASK] update Xilinx directIO examples

Cleanup and set packet buffer higher 1 GB

Change-Id: I0da8d530c5bcb5a5cb76ea7ee4162036721d04ac
[FIX] MN allocates asynchronous slot to itself but sends no message

Add error handling when Asnd TX buffer is not ready which reverts the
invitation in the SoA packet.

Change-Id: Ie270cc497a8578280b5bf30374f181d793f2a1d7
[FEATURE] add benchmark IO for qsys subsystem "pcp_0"

Change-Id: I41d98fc56b6cb21303926ff628915a69cc2c6afa
[TASK] create fpga and Examples/arch for fpga demos

Change-Id: I30480526b2959b04ec7eaa9971bbe4556788af22
[TASK] adjust new directory structure in Altera and Xilinx demos

Change-Id: I41c92b979bc1e1514acf2a23ce4a1cf9f5a44fe7
[TASK] Refactor DLL CAL module (1)

Remove call to DllkCalAsyncSend in EplDlluCal.c and moved direct calls
and shared buffer from EplDll*Cal to EplDllCalDirect and EplDllCalShb.

Implemented TX packet forwarding:
* direct calls
* shared buffer

Change-Id: Ifb6fb773e9c5ec687c060790b82cbe21d681fd87
[TASK] Refactor DLL CAL module (2)

Adapt DLL CAL files for new directory structure and
correct all build files.

Change-Id: Iad2e76b6debe6c11f92a4a0110bcca67bc16e51b
[TASK] Refactor DLL CAL module (3)

Refactor DLL CAL module to use function pointers to use different
implementations for different queues. Cleanup function and variable
names.

Change-Id: I97e4f8cbb23291f16226b1524f0b9e96173c1261
[FEATURE] revised event handling approach with cal

The new event handling approach uses Event*cal to abstract the event posting.
Note that the layer queues' consumer post the received events into the
layer internal queues (K2U -> Uint and U2K -> Kint).

The following event forwarding is implemented:
* direct calls
* shared buffer

Change-Id: Ib8b8cea4f7ead3fdbda16b0ec6dff114e09e6540
[TASK] Refactor event handler - Rename Files

Rename files and organize them in new directory structure.

Change-Id: I2e36110cad3dfaa7d076cbc0dce22a07246578f7