update board_part of current project even if not generating PCIE core

Change-Id: Iae8c17ea89a37eda534ea698251168e7dd1d8994
if project contains synth-ip.tcl, source that before synthesis

Change-Id: I0d4edbb1b08b356d3aa914723f2ac04e95ed2364
use xbsv_synth_ip to generate the pcie core if it is needed

Change-Id: Iacf139a5c3de37646f3b3bea1f26d899e52ca85b