First cut at an HSI configuration API for rcc on the STMF4 series.

This is a first cut at a simplified setup function for the HSI clock on the STM32F series. The function is called simply `rcc_set_hsi_clock(uint32_t speed)` and it takes 32 bit constant which has encoded the PLL values to achieve that speed.  It is possible to generalize it to something even more generic, one could have `rcc_set_pll_clock(uint32_t pll_constants, uint32_t base_frequency);` where the  `pll constants` would have been set for an HSE or HSI input, and `base_frequency` would be the starting crystal frequency. But that is prone to error is you used HSI PLL flags and an HSE crystal for example. 

Two things I do like is that it automatically computes the best APB2 and APB1 clocks. This avoids problems where the constants don't match the setup and things like the UARTs don't get the right baud rate constants. It also automatically sets the FLASH wait states based on the data sheet. I did consider making the FLASH wait state value a parameter so that it is completely general purpose at all voltages for HSI. 
In some architectures there are multiple PLL sources, and it is almost
possible to put the clock setup code in one common rcc_all.c file, I'm
hoping to get to that point.

On Mon, Dec 22, 2014 at 10:58 AM, Karl Palsson <notifications@github.com>
wrote:
>
> In include/libopencm3/stm32/f4/rcc.h
> <https://github.com/libopencm3/libopencm3/pull/379#discussion-diff-22183142>
> :
>
> >  #define RCC_PLLCFGR_PLLSRC			(1 << 22)
> > +#define RCC_PLLCFGR_PLLSRC_MASK			1
> > +#define RCC_PLLCFGR_PLLSRC_SHIFT		22
>
> I *really* don't think we need shift and mask defines for single bit
> positions.
>
> —
> Reply to this email directly or view it on GitHub
> <https://github.com/libopencm3/libopencm3/pull/379/files#r22183142>.
>