Add missing line breaks to debug output in CodeGenPrepare

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208731 91177308-0d34-0410-b5e6-96231b3b80d8
[RuntimeDyld] Fix handling of i386 PC-rel external relocations. This fixes
several more i386 MCJIT regression test failures.

<rdar://problem/16889891>



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[tools][llvm-rtdyld] Add a '-dylib <file>' option to llvm-rtdyld to load shared
libraries before linking and executing the target objects.

This allows programs that use external calls (e.g. to libc) to be run under
llvm-rtdyld.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208739 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Try to fix BFE operands when moving to VALU

This was broken by r208479

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Fix typo in function name.

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Recommit r208506: DebugInfo: Include lexical scopes in inlined subroutines.

This was reverted in r208642 due to regressions surrounding file changes
within lexical scopes causing inlining information to be lost.

The issue was in LexicalScopes::getOrCreateInlinedScope, where I was
previously testing "isLexicalBlock" which is false for
"DILexicalBlockFile" (a scope used to represent changes in the current
file name) and assuming it was then a function (breaking out of the
inlined scope path and reaching for the parent non-inlined scopes). By
inverting the condition and testing for "isSubprogram" the correct
behavior is attained.

(also found some weirdness in Clang, see r208742 when reducing this test
case - the resulting test case doesn't apply with the Clang fix, but
I've added a more realistic test case to inline-scopes.ll which does
reproduce the issue and demonstrate the fix)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208748 91177308-0d34-0410-b5e6-96231b3b80d8
Optimize integral reciprocal (udiv 1, x and sdiv 1, x) to not use division. This fires exactly once in a clang bootstrap, but covers a few different results from http://www.cs.utah.edu/~regehr/souper/


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208750 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: implement support for the UDF mnemonic

The UDF instruction is a reserved undefined instruction space.  The assembler
mnemonic was introduced with ARM ARM rev C.a.  The instruction is not predicated
and the immediate constant is ignored by the CPU.  Add support for the three
encodings for this instruction.

The changes to the invalid instruction test is due to the fact that the invalid
instructions actually overlap with the undefined instruction.  Introduction of
the new instruction results in a partial decode as an undefined sequence.  Drop
the tests as they are invalid instruction patterns anyways.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208751 91177308-0d34-0410-b5e6-96231b3b80d8
[obj2yaml] Support ELF input format in the obj2yaml tool.

The ELF header e_flags field in the MIPS related test cases handled
incorrectly. The obj2yaml prints too many flags. I will fix that in the
next patches.

The patch reviewed by Michael Spencer and Sean Silva.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208752 91177308-0d34-0410-b5e6-96231b3b80d8
Update the comments for ComputeMaskedBits, which lost its Mask parameter
in r154011.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208757 91177308-0d34-0410-b5e6-96231b3b80d8
Fix strange typo in markup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208759 91177308-0d34-0410-b5e6-96231b3b80d8
Fix the case when reordering shuffle and binop produces a constant.

This resolves PR19737.


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Update of the documentation: I think we are now happy with Phabricator

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[asan] Set debug location in ASan function prologue.

Most importantly, it gives debug location info to the coverage callback.

This change also removes 2 cases of unnecessary setDebugLoc when IRBuilder
is created with the same debug location.



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[asan] Fix compiler warnings.


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Regression test for ARM EHABI breakage in r208166.


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ARM64: remove unneeded InstPrinter hacks

Now that TableGen handles aliases, these are unneeded. Hopefully more will be
able to go soon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208781 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][mips64r6] Add sel.s and sel.d

Summary:
Also use named constants for common opcode fields.

Depends on D3669

Reviewers: vmedic, zoran.jovanovic, jkolek

Reviewed By: jkolek

Differential Revision: http://reviews.llvm.org/D3670

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[mips] Test that IAS for -mcpu=mips5 does not accept MIPS64 insns and -mcpu=mips(5|64) does not accept MIPS64r2

Summary:
To limit the number of tests required, only one 64-bit ISA prior to MIPS64 are tested.

rdhwr has been deliberately left without an ISA annotation for now. This is
because the assembler and CodeGen disagree on when the instruction is
available. Strictly speaking, it is only available in MIPS32r2 and
MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is
necessary for TLS so CodeGen should emit it on older ISA's too.

Depends on D3697

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3698

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X86: If we have an instruction that sets a flag and a zero test on the input of that instruction try to eliminate the test.

For example
	tzcntl	%edi, %ebx
	testl %edi, %edi
	je	.label

can be rewritten into
	tzcntl	%edi, %ebx
	jb 	.label

A minor complication is that tzcnt sets CF instead of ZF when the input
is zero, we have to rewrite users of the flags from ZF to CF. Currently
we recognize patterns using lzcnt, tzcnt and popcnt.

Differential Revision: http://reviews.llvm.org/D3454

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