Optimize delay in instruction fetch logic

There was a very long combinational path that chose the next PC to fetch.
It was attempting to not increment the PC when a cache miss occurred, but
this made the PC dependent on the cache_hit signal in the next stage (which
in turn actually checked the incoming L2 response to look for a near miss).
The new implementation always advances the program counter when a fetch
is requested, but decrements it when a cache miss occurs.