hdl: add RX and TX meta FIFOs

These FIFOs will be used to store timestamp, modulation, and coding data
on a per packet basis. The meta header format is described in the
following commit.
hdl: timed RX and TX

Timed RX and TX is enabled when nios_gpio bit 9 is set. RX and TX samples
are now packetized so now the first 16 bytes of every 512 byte or 1024
byte GPIF transcations contain metadata. The HDL state machine will not
wait for the TX time to match that of any TX packet, and it will insert
timestamps into RX packet streams.
hdl: add time tamer

This tamer is an Avalon compatible core that snapshots the RX and TX timestamp
counters whenever the least significant byte of the 64bit registers is read.
The RX LSB is at offset 0, and the TX LSB is at offset 8. If any register within
the time tamer address space is writen to, the core will output a sync signal
that the rest of the system will interpret as a signal to synchronize resetting
the RX and TX timestamp counters to 0.
hdl: minor corrections needed to get testbench working again
nios: rework register mapping

This commit adds support for time tamer register and introduces a command
parsing loop that allows for multiple reads/write per uart_cmd packet.
libbladeRF: add variable length memory register reads/writes

This commit adds support for performing an arbitrary number of reads/writes when
accessing memory mapped registers inside of Nios.
The 8 byte timestamp counters can now be read in 2 uart_cmd packets instead of 8.
libbladeRF: add the ability to query RX and TX timestamp counters