Fix non-IEEE mode

This is done by avoiding CVTSS2SD/CVTSD2SS for float conversions and instead using FLD+FSTP followed by some instructions for resetting the QNaN bit to its original value.

I haven't done any performance testing yet of the QNaN reset code yet. According to Intel, mixing float and integer SSE instructions carries some performance penalty.

Thanks to @phire for pointing out both pitfalls.