unittests: Actually test reverse iterators in Path tests

This re-enables some #if 0'd code (since 2010) in the Path unittests
and makes at least a weak effort at testing sys::path's rbegin/rend.

This change was inspired by some test failures near uses of rbegin and
rend here:

    http://lab.llvm.org:8011/builders/clang-x86_64-linux-vg/builds/3209

The "valgrind was whining" comment looked promising in terms of a
simpler to debug case of the same errors. However, it appears that the
valgrind complaints the comment was referring to are distinct from the
ones in the frontend, since this updated test isn't complaining for me
under valgrind.

In any case, the disabled tests weren't helping anybody.

git-svn-id: http://llvm.org/svn/llvm-project/llvm/trunk@213125 91177308-0d34-0410-b5e6-96231b3b80d8
[X86] Add a check for 'isMOVHLPSMask' within method 'isShuffleMaskLegal'.

Before this change, method 'isShuffleMaskLegal' didn't know that shuffles
implementing a 'movhlps' operation were perfectly legal for SSE targets.

This patch adds the missing check for 'isMOVHLPSMask' inside method
'isShuffleMaskLegal' to fix the problem.

The reason why it is important to do this is because the DAGCombiner
conservatively avoids combining a pair of shuffles if the resulting shuffle
node has an illegal mask. Before this patch, shuffles with a MOVHLPS mask were
wrongly considered not to be legal. This was the root cause of some poor-code
generation bugs.



git-svn-id: http://llvm.org/svn/llvm-project/llvm/trunk@213137 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][fp64a] Temporarily disable odd-numbered double-precision registers when using the FP64A ABI.

Summary:
A few instructions (mostly cvt.d.w and similar) are causing problems with
-mfp64 and -mno-odd-spreg and it looks like fixing it properly may
take several weeks. In the meantime, let's disable the odd-numbered
double-precision registers so that the generated code is at least valid.

The problem is that instructions like cvt.d.w read from the 32-bit low
subregister of a double-precision FPU register. This often leads to the compiler
to inserting moves to transfer a GPR32 to a FGR32 using mtc1. Such moves
violate the rules against 32-bit writes to odd-numbered FPU registers imposed
by -mno-odd-spreg. By disabling the odd-numbered double-precision registers, it
becomes impossible for the 32-bit low subregister to be odd-numbered.

This fixes numerous test-suite failures when compiling for the FP64A ABI
('-mfp64 -mno-odd-spreg'). There is no LLVM test case because it's difficult to
test that odd-numbered FPU registers are not allocatable. Instead, we depend on
the assembler (GAS and -fintegrated-as) raising errors when the rules are
violated.

Differential Revision: http://reviews.llvm.org/D4532


git-svn-id: http://llvm.org/svn/llvm-project/llvm/trunk@213160 91177308-0d34-0410-b5e6-96231b3b80d8
Convert test to CHECK-LABEL

git-svn-id: http://llvm.org/svn/llvm-project/llvm/trunk@213161 91177308-0d34-0410-b5e6-96231b3b80d8
CodeGen: don't form illegail EXTLOAD operations.

It turns out that in most cases (the main exception being i1-related
types) once these operations are formed we cannot separate them and
the targets end up having to deal with them whether they want to or
not.

This is not a good situation, and a more reasonable default can be
formed by ackowledging this and having targets leave them as Legal.
Only x86 seems to be affected (other targets don't even try marking
the operation Expand).

Mostly there's no visible change here yet, but it will be useful to
have truly expanded EXTLOADS for MVT::f16 softening support.

git-svn-id: http://llvm.org/svn/llvm-project/llvm/trunk@213162 91177308-0d34-0410-b5e6-96231b3b80d8
[NVPTX] Rename registers %fl -> %fd and %rl -> %rd

This matches the internal behavior of NVIDIA tools like libnvvm.

git-svn-id: http://llvm.org/svn/llvm-project/llvm/trunk@213168 91177308-0d34-0410-b5e6-96231b3b80d8
Added documentation for SizeMultiplier in the ARM subtarget hook for register coalescing. Also fixed some 80 col violations.

No functional code changes.

git-svn-id: http://llvm.org/svn/llvm-project/llvm/trunk@213169 91177308-0d34-0410-b5e6-96231b3b80d8
Track clang r213171

The clang rewriter is now a core facility.

git-svn-id: http://llvm.org/svn/llvm-project/llvm/trunk@213173 91177308-0d34-0410-b5e6-96231b3b80d8
Remove unnecessary/redundant std::move

(run returns unique_ptr by value already)

git-svn-id: http://llvm.org/svn/llvm-project/llvm/trunk@213174 91177308-0d34-0410-b5e6-96231b3b80d8
Add the "-x" flag to llvm-nm for Mach-O files that prints the fields of a symbol in hex.
(generally use for debugging the tools).  This is same functionality as darwin’s
nm(1) "-x" flag.


git-svn-id: http://llvm.org/svn/llvm-project/llvm/trunk@213176 91177308-0d34-0410-b5e6-96231b3b80d8
CHECK-LABEL-ize one test

git-svn-id: http://llvm.org/svn/llvm-project/llvm/trunk@213177 91177308-0d34-0410-b5e6-96231b3b80d8
[NVPTX] Honor alignment on vector loads/stores

We were not considering the stated alignment on vector loads/stores,
leading us to generate vector instructions even when we do not have
sufficient alignment.

Now, for IR like:

  %1 = load <4 x float>, <4 x float>* %ptr, align 4

we will generate correct, conservative PTX like:

  ld.f32 ... [%ptr]
  ld.f32 ... [%ptr+4]
  ld.f32 ... [%ptr+8]
  ld.f32 ... [%ptr+12]

Or if we have an alignment of 8 (for example), we can
generate code like:

  ld.v2.f32 ... [%ptr]
  ld.v2.f32 ... [%ptr+8]

git-svn-id: http://llvm.org/svn/llvm-project/llvm/trunk@213186 91177308-0d34-0410-b5e6-96231b3b80d8
[RegisterCoalescer] Moving the RegisterCoalescer subtarget hook onto the TargetRegisterInfo instead of the TargetSubtargetInfo.

git-svn-id: http://llvm.org/svn/llvm-project/llvm/trunk@213188 91177308-0d34-0410-b5e6-96231b3b80d8
Utilize CastInst::CreatePointerBitCastOrAddrSpaceCast here.


git-svn-id: http://llvm.org/svn/llvm-project/llvm/trunk@213189 91177308-0d34-0410-b5e6-96231b3b80d8
Remove Atom references in description.

Any CPU can run this pass.


git-svn-id: http://llvm.org/svn/llvm-project/llvm/trunk@213190 91177308-0d34-0410-b5e6-96231b3b80d8
trivial fix for PR20314

Make sure that the AddrInst is an Instruction.


git-svn-id: http://llvm.org/svn/llvm-project/llvm/trunk@213197 91177308-0d34-0410-b5e6-96231b3b80d8
Fix a typo in the inalloca description

git-svn-id: http://llvm.org/svn/llvm-project/llvm/trunk@213200 91177308-0d34-0410-b5e6-96231b3b80d8
[MCJIT] Improve a RuntimeDyldChecker diagnostic.

When a RuntimeDyldChecker test requests an invalid operand for an instruction,
print the decoded instruction to aid diagnosis.



git-svn-id: http://llvm.org/svn/llvm-project/llvm/trunk@213202 91177308-0d34-0410-b5e6-96231b3b80d8
[FastISel] Local values shouldn't be alive across an inline asm call with side effects.

This fixes an issue where a local value is defined before and used after an
inline asm call with side effects.

This fix simply flushes the local value map, which updates the insertion point
for the inline asm call to be above any previously defined local values.

This fixes <rdar://problem/17694203>

git-svn-id: http://llvm.org/svn/llvm-project/llvm/trunk@213203 91177308-0d34-0410-b5e6-96231b3b80d8
Fixed formatting, removed bug reference, renamed testcase

Thanks to Duncan Exon Smith for reviewing and cleanup suggestions. 


git-svn-id: http://llvm.org/svn/llvm-project/llvm/trunk@213205 91177308-0d34-0410-b5e6-96231b3b80d8