Fix comments and code snippets that were making incorrect claims about
the alignment requirement of the guest state, shadow areas, and register
spill area sizes.
The size of these areas ought to be a multiple of 16 bytes.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2818 8f6e269a-dfd6-0310-a8e1-e2731360e62c
mips64: add support for load indexed instructions from DSP ASE

Handling lwx, ldx and lbux for MIPS-Cavium processors.

Patch by Zahid Anwar, with some changes.

Related to Bugzilla issue 326444.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2819 8f6e269a-dfd6-0310-a8e1-e2731360e62c