Prevented location preprocessor to confuse VHDL assertions with severity warning, error, or failure with log calls with the same names.
Added script for generating the various check_equal combinations.
Changed check_equal error messages to include both vector and integer representations of the left and right operands when at least one operand is a vector. Made
vectors representations more readable by separating nibbles with underscore.
Removed overflow warnings from tb_string_ops.vhd when using exponentiation.
Added support for displaying the full vector representation of integers/naturals in check_equal error messages even when the vector with which the integer/natural is compared has a length shorter than what's needed to house the integer/natural.
Added support for verilog files at ui.py level.
File type is automatically detected based on file ending.
Improved error message for unknown file endings
Fixes #6 by catching exception when removing output path
Placing modelsim transcript files in vunit folders.
Added explicit location of wlf file as tests/test_xxx/msim/vsim.wlf
Made add_config more explicit
Removed backslashes from wlf file path.
Added license header check for Verilog and System Verilog files.
Initial version of the check_preprocessor. Fokus on parser and its limitations. Tool integration needs more work.
Updated check_example.vhd with how impure functions can be handled when using check_relation.
Enabled preprocessors to be specified on a per file basis. Added the possibility to add custom preprocessors.Added missing files and added some more check_relation examples.