fdt_support: split fdt_getprop_u32_default

We already have a nice helper to give us a property cell value with default
fall back from a path. Split that into two helpers - one for the old path
based lookup and one to give us a value based on a node offset.

Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
fdt_support: Add helper function to read "ranges" property

This patch adds a helper function that can be used to interpret most
"ranges" properties in the device tree.

It reads the n'th range out of a "ranges" array and returns the node's
virtual address of the range, the physical address that range starts at
and the size of the range.

Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
PPC: 85xx: Remove IVOR reset

There is no need to set IVORs to anything but their default values,
so let's leave them where they are.

Suggested-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Scott Wood <scottwood@freescale.com>
[York Sun: Add back $(obj)start.S section in mpc8572ds/Makefile]
Reviewed-by: York Sun <yorksun@freescale.com>
PPC: 85xx: Generalize DDR TLB mapping function

The DDR mapping function really is just a generic virtual -> physical
mapping function. Generalize it so it can support any virtual starting
offset and IO maps just the same.

Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
PPC 85xx: Add ELF entry point

We want to be able to directly execute the ELF binary without going
through the u-boot.bin one.

To know where we have to start executing this ELF binary  we have to
tell the linker where our entry point is.

Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
PPC 85xx: Add qemu-ppce500 machine

For KVM we have a special PV machine type called "ppce500". This machine
is inspired by the MPC8544DS board, but implements a lot less features
than that one.

It also provides more PCI slots and is supposed to be enumerated by
device tree only.

This patch adds support for the generic ppce500 machine and tries to
rely solely on device tree for device enumeration.

Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
fsl/usb: Fix phy type for Second USB controller

Set correct phy_type value for second USB controller.
This is required for supporting SOCs having 2 USB controllers
working simultaneously, one with UTMI phy and other with ULPI phy

Signed-off-by: Nikhil Badola <B46172@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
powerpc/p1010rdb: SECURE BOOT enabled for NAND

In case of secure boot from NAND, the DDR is initialized by the
BootROM using the config words (CF_WORDS) in the CF_HEADER
and u-boot image is copied from NAND to DDR by the BootROM.
So, CONFIG_SYS_RAMBOOT has been defined for Secure Boot from NAND.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
powerpc/p1010rdb: SECURE BOOT- enable workaround for IFC errata A003399

The workaround for IFC errata A003399 was not enabled
in case of secure boot. So, secure boot from NOR was not
working.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
powerpc/mpc8xxx: SECURE BOOT- Disable law 0 for non PBL platforms

ISBC creates a LAW 0 entry for non PBL platforms, which is not
disabled before transferring the control to uboot.
The LAW 0 entry has to be disabled.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for BSC9132QDS

Add NOR, SPI and SD secure boot targets for BSC9132QDS.

Changes:
- Debug TLB entry is not required for Secure Boot Target.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
powerpc/mpc85xx: SECURE BOOT- Add NAND secure boot target for BSC9132QDS

In case of secure boot from NAND, the DDR is initialized by the
BootROM using the config words (CF_WORDS) in the CF_HEADER
and u-boot image is copied from NAND to DDR by the BootROM.
So, CONFIG_SYS_RAMBOOT has been defined for Secure Boot from NAND

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS

Changes:
1. L2 cache is being invalidated by Boot ROM code for e6500 core.
   So removing the invalidation from start.S
2. Clear the LAW and corresponding configuration for CPC. Boot ROM
   code uses it as hosekeeping area.
3. For Secure boot, CPC is configured as SRAM and used as house
   keeping area. This configuration is to be disabled once in uboot.
   Earlier this disabling of CPC as SRAM was happening in cpu_init_r.
   As a result cache invalidation function was getting skipped in
   case CPC is configured as SRAM.This was causing random crashes.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T4240QDS and T4160QDS

Secure Boot Target is added for T4240QDS and T4160QDS
Changes:
For Secure boot, CPC is configured as SRAM and used as house
keeping area which needs to be disabled.
So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T4240QDS.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080QDS

Secure Boot Target is added for T2080QDS
Changes:
For Secure boot, CPC is configured as SRAM and used as house
keeping area which needs to be disabled.
So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080QDS.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T1040QDS and T1040RDB

Secure Boot Target is added for T1040QDS and T1040RDB
Changes:
For Secure boot, CPC is configured as SRAM and used as house
keeping area which needs to be disabled.
So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T1040QDS and
CONFIG_T1040RDB

Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
QE/FMAN: modify CONFIG_SYS_QE_FMAN_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR and CONFIG_SYS_QE_FW_ADDR

CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address.
Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address,
and CONFIG_SYS_QE_FW_ADDR for QE microcode address.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
QE/U-QE: Add U-QE support

Modify code to adapt to both u-qe and qe.

U_QE is a kind of cutted QE.
the differences between U_QE and QE
	1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs.
	2. IMMR: have different immr base addr.
	3. iopin: U_QE doesn't need to config iopin.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
t1040rdb/qe: add QE support for T1040RDB

add CONFIG_QE, CONFIG_U_QE and CONFIG_SYS_QE_FW_ADDR into
"include/configs/T1040RDB.h"

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
board/b4860qds:Slow MDC clock to comply IEEE specs in PBI config

The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher
than 2.5 MHZ.  It violates the IEEE specs.

So Slow MDC clock to comply IEEE specs

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>