check for options.bitfile
fixed plainModuleRe to allow whitespace between instance name and open paren
skip verilog keywords
added debug option
expand subdirectories of vpath
do not assume source is in ./verilog/
added header file option
improved module matching
added header files to Makefile.fpgamake.common
look for upper and lower case variants of file name
use find_in_path to find module verilog
adding support for vhdl