new project to test ram signals
Merge branch 'master' of https://github.com/fpga-logi/Logi-projects
python wrapper for the IMU
updated pin definitions for board version RA.1.
adding built .bit files to test a range of frequencies
new version with corrected gyro reading
Merge branch 'master' of https://github.com/fpga-logi/Logi-projects
added pwm_gen.bit file
new project to tes sdram of logibone, still under development (missing UCF and test_bench to validate FSM)
slamm changes, bug found while testing
added simulation model of the SDRAM
new testbench fo full design
PWM_VHDL
Merge branch 'master' of https://github.com/fpga-logi/Logi-projects
Updated UCF - built and ran - seems to hang
error on reset line
Merge branch 'master' of https://github.com/fpga-logi/Logi-projects
using my changes
Conflicts:
	logibone-sdram_test/logibone-sdram_test.gise
	logibone-sdram_test/logibone-sdram_test.xise
major change on clock phase !
improved clock
model now simulating well and test pass