added input/output bus widths
test commit
record keeping
finished first draft scalar reg file
removed random test wire
Vector Register File\!
added a space
started VADD module
testing Merge branch 'Max' into Matt
rewrote scalar reg file and continued with ALU
Two phase overlapping clock source module
finished step 1 and 2 from http://www.cs.umd.edu/class/sum2003/cmsc311/Notes/BinMath/addFloat.html for VADD
Untested DRAM written
first pass VADD complete
Update .gitignore

Added tilde
merge Max into master
Put the DRAM through a single test; It worked\!
Merge branch 'Max'
Second message confirming that Matt merged his changes into master
Post merge