Update Verilog to accommodate IRQs

Top Level GPU used improper signal (fifo_full_o instead of fifo_full)
Added logic to tb to mimic how the IRQ will work on the SoC:
Every IRQ causes a FIFO Full variable to change status. First IRQ
means empty, second full, third empty, and so on.
Change dimensions to 640x480
Add entries to .gitignore
Add gpu_irq_generator and edge_detect to makefile