msm: bam_dmux: UL inactivity timeout is too high

Reduce UL_TIMEOUT from 1000 ms to 200 ms to improve current drain
for idle use case.

Change-Id: I83eba12e28506735ff15f52533dda653872fc9f2
Signed-off-by: Alexander Filonenko <vtp684@motorola.com>
Reviewed-on: http://gerrit.pcs.mot.com/538334
Tested-by: Jira Key <jirakey@motorola.com>
Reviewed-by: Connie Zhao <czhao1@motorola.com>
Reviewed-by: Check Patch <CHEKPACH@motorola.com>
Reviewed-by: Klocwork kwcheck <klocwork-kwcheck@sourceforge.mot.com>
Submit-Approved: Jira Key <jirakey@motorola.com>
Reviewed-by: Igor Kovalenko <cik009@motorola.com>
Reviewed-by: Christopher Fries <c.fries@motorola.com>
SLT-Approved: Christopher Fries <c.fries@motorola.com>
Delay UL powerdown if BAM is in polling mode

Change-Id: I982c669863390d5ea828d8dd3158e76dab3163e9
Reviewed-on: http://gerrit.pcs.mot.com/548359
Tested-by: Jira Key <jirakey@motorola.com>
Reviewed-by: Igor Kovalenko <cik009@motorola.com>
Reviewed-by: Klocwork kwcheck <klocwork-kwcheck@sourceforge.mot.com>
Reviewed-by: Alexander Filonenko <alexf@motorola.com>
SLT-Approved: Christopher Fries <c.fries@motorola.com>
Submit-Approved: Jira Key <jirakey@motorola.com>
msm: bam_dmux: optimize UL inactivity timeout

Increase UL_TIMEOUT_DELAY to 300 ms to avoid most of powerdown attempts while
in polling mode.

Change-Id: Ibbcf641caac492357f78c1d6fd378609ea546c67
Signed-off-by: Alexander Filonenko <vtp684@motorola.com>
Reviewed-on: http://gerrit.pcs.mot.com/548732
Tested-by: Jira Key <jirakey@motorola.com>
Reviewed-by: Check Patch <CHEKPACH@motorola.com>
Reviewed-by: Klocwork kwcheck <klocwork-kwcheck@sourceforge.mot.com>
Reviewed-by: Igor Kovalenko <cik009@motorola.com>
SLT-Approved: Christopher Fries <c.fries@motorola.com>
Submit-Approved: Jira Key <jirakey@motorola.com>
msm: bam_dmux: fix compilation issue

Change-Id: Ie4dd92ce622a1e59bd415b0d8ba25c1896b20fab
Signed-off-by: Jeffrey Carlyle <jeff.carlyle@motorola.com>

Conflicts:
	arch/arm/mach-msm/bam_dmux.c
msm: bam_dmux: Remove SSR after shutdown_completion timeout

The modem restart introduced by following commit
3d04101 msm: bam_dmux: delay shutdown until DL polling is complete
is seen to be called incorrectly even when modem is up normally.

Avoid condition by:
1) Removed SSR upon shutdown completetion timeout to make
   behaviour similar to previous releases
2) Increased the SHUTDOWN_TIMEOUT_MS from 500ms to 2s as per QC suggestion

Change-Id: Ic7b9f5661b8eed8b12455a4295ff1b738e6a76b7
Signed-off-by: A. Kaul <w42726@motorola.com>
Reviewed-on: http://gerrit.pcs.mot.com/624505
SLTApproved: Slta Waiver <sltawvr@motorola.com>
Tested-by: Jira Key <jirakey@motorola.com>
Reviewed-by: Jayachandran Chinnakkannu <jayc@motorola.com>
Reviewed-by: Christopher Fries <c.fries@motorola.com>
Submit-Approved: Maulik Desai <amd093@motorola.com>
(cherry picked from commit 55b2454d4b0b0c1e81b20fdca88d5dd02021fb2c)
Reviewed-on: http://gerrit.pcs.mot.com/625599
Reviewed-by: Upgrade Build <dbbuild@motorola.com>
SLTApproved: Upgrade Build <dbbuild@motorola.com>
Submit-Approved: Upgrade Build <dbbuild@motorola.com>
Tested-by: Upgrade Build <dbbuild@motorola.com>
Merge branch 'dev' into my-aospv2-4.4
CPUFREQ Alucard GOV: small tune of cpus_down_rate to reduce idle drain.

*I see that any small app that create small load < 10% make gov
to rise freqs too high without any need.
so drain on idle + music app is higher than expected.
also heat building up without need.

this change effect bench testes on low load, for 1 fps.
but battery is more important.
asm-generic: io: don't perform swab during {in,out} string functions

The {in,out}s{b,w,l} functions are designed to operate on a stream of
bytes and therefore should not perform any byte-swapping, regardless of
the CPU byte order.

This patch fixes the generic IO header so that {in,out}s{b,w,l} call the
__raw_{read,write} functions directly rather than going via the
endian-correcting accessors.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Ben Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
ARM: nommu: provide dummy cpu_switch_mm implementation

cpu_switch_mm is a logical nop on nommu systems, so define it as such
when !CONFIG_MMU.

Signed-off-by: Will Deacon <will.deacon@arm.com>
ARM: mpu: add PMSA related registers and bitfields to existing headers

This patch adds the following definitions relevant to the PMSA:

Add SCTLR bit 17, (CR_BR - Background Region bit) to the list of CR_*
bitfields. This bit determines whether to use the architecturally defined
memory map

Add the MPUIR to the available registers when using read_cpuid macro. The
MPUIR is the MPU type register.

Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
CC:"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>
Signed-off-by: Jake Weinstein <xboxlover360@gmail.com>
ARM: mpu: add header for MPU register layouts and region data

This commit adds definitions relevant to the ARM v7 PMSA compliant MPU.

The register layouts and region configuration data is made accessible to asm
as well as C-code so that it can be used in early bring-up of the MPU.

The mpu region information structs assume that the properties for the I/D side
are the same, though the implementation could be trivially extended for future
platforms where this is no-longer true.

The MPU_*_REGION defines are used for the basic, static MPU region setup.

Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Jake Weinstein <xboxlover360@gmail.com>
ARM: mpu: add early bring-up code for the ARMv7 PMSA-compliant MPU

This patch adds initial support for using the MPU, which is necessary for
SMP operation on PMSAv7 processors because it is the only way to ensure
memory is shared. This is an initial patch and full SMP support is added
later in this series.

The setup of the MPU is performed in a way analagous to that for the MMU:
Very early initialisation before the C environment is brought up, followed
by a sanity check and more complete initialisation in C.

This patch provides the simplest possible memory region configuration:
MPU_PROBE_REGION: Reserved for probing MPU details, not enabled
MPU_BG_REGION: A 'background' region that specifies all memory strongly ordered
MPU_RAM_REGION: A single shared, cacheable, normal region for the valid RAM.

In this early initialisation code we simply map the whole of the address
space with the BG_REGION and (at least) the kernel with the RAM_REGION. The
MPU has region alignment constraints that require us to round past the end
of the kernel.

As region 2 has a higher priority than region 1, it overrides the strongly-
ordered behaviour for RAM only.

Subsequent patches will add more complete initialisation from the C-world
and support for bringing up secondary CPUs.

Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
CC: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Jake Weinstein <xboxlover360@gmail.com>

Conflicts:
	arch/arm/kernel/head-nommu.S
ARM: mpu: add MPU initialisation for secondary cores

The MPU initialisation on the primary core is performed in two stages, one
minimal stage to ensure the CPU can boot and a second one after
sanity_check_meminfo. As the memory configuration is known by the time we
boot secondary cores only a single step is necessary, provided the values
for DRSR are passed to secondaries.

This patch implements this arrangement. The configuration generated for the
MPU regions is made available to the secondary core, which can then use the
asm MPU intialisation code to program a complete region configuration.

This is necessary for SMP configurations without an MMU, as the MPU
initialisation is the only way to ensure that memory is specified as
'shared'.

Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
CC: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Jake Weinstein <xboxlover360@gmail.com>
ARM: prefetch: remove redundant "cc" clobber

The pld instruction does not affect the condition flags, so don't bother
clobbering them.

Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
ARM: atomics: prefetch the destination word for write prior to strex

The cost of changing a cacheline from shared to exclusive state can be
significant, especially when this is triggered by an exclusive store,
since it may result in having to retry the transaction.

This patch prefixes our atomic access implementations with pldw
instructions (on CPUs which support them) to try and grab the line in
exclusive state from the start. Only the barrier-less functions are
updated, since memory barriers can limit the usefulness of prefetching
data.

Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
ARM: atomic64: fix endian-ness in atomic.h

Fix inline asm for atomic64_xxx functions in arm atomic.h. Instead of
%H operand specifiers code should use %Q for least significant part
of the value, and %R for the most significant part of the value. %H
always returns the higher of the two register numbers, and therefore
it is not endian neutral. %H should be used with ldrexd and strexd
instructions.

Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
ARM: 7983/1: atomics: implement a better __atomic_add_unless for v6+

Looking at perf profiles of multi-threaded hackbench runs, a significant
performance hit appears to manifest from the cmpxchg loop used to
implement the 32-bit atomic_add_unless function. This can be mitigated
by writing a direct implementation of __atomic_add_unless which doesn't
require iteration outside of the atomic operation.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: 7447/1: rwlocks: remove unused branch labels from trylock routines

The ARM arch_{read,write}_trylock implementations include unused
backwards branch labels, since we don't retry the locking operation
if the exclusive store fails.

This patch removes the labels.

Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: nommu: define dummy TLB operations for nommu configurations

nommu platforms do not perform address translation and therefore clearly
don't have TLBs. However, some SMP code assumes the presence of the TLB
flushing routines and will therefore fail to compile for a nommu system.

This patch defines dummy local_* TLB operations and #defines
tlb_ops_need_broadcast() as 0, therefore causing the usual ARM SMP TLB
operations to call the local variants instead.

Signed-off-by: Will Deacon <will.deacon@arm.com>
CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
CC: Nicolas Pitre <nico@linaro.org>
ARM: nommu: add stub local_flush_bp_all() for !CONFIG_MMUU

Since the merging of Will's tlb-ops branch, specifically 89c7e4b8bbb3
(ARM: 7661/1: mm: perform explicit branch predictor maintenance when required),
building SMP without CONFIG_MMU has been broken.

The local_flush_bp_all function is only called for operations related to
changing the kernel's view of memory and ASID rollover - both of which are
irrelevant to an !MMU kernel.

This patch adds a stub local_flush_bp_all() function to the other tlb
maintenance stubs and restores the ability to build an SMP !MMU kernel.

Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>