defconfig: Update

Signed-off-by: Kostas K <mpokwsths@gmail.com>
msm: clock-8974: Support 8974ac frequency plan

Update frequency tables and fmax settings for certain
clocks to match the latest 8974ac frequency plan data.

Change-Id: Iad9d7485eeae0c9f21f5829a96fab355fa575bd2
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
msm: clock-8974: Fix 8974ac gpll4 and mclk changes

GPLL4 only exists on v3 variants, and shouldn't be in the lookup table
for v1/v2.  Camera MCLK is changed to match its clock type.

Change-Id: Id15313bfcaed783f7f835ff75f651e38d4bad8de
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
msm: devfreq_cpubw: Add devfreq driver for CPU to DDR bandwidth voting

This driver registers itself as a devfreq device that allows devfreq
governors to make CPU to DDR IB/AB bandwidth votes. This driver allows the
governors to be agnostic of the bandwidth voting APIs, the number of CPU
master ports or DDR slave ports, the actual port numbers, the system
topology, the available DDR frequencies, etc.

Change-Id: If055ddd580afd41f9668b111e6c09a047488b2e0
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
(cherry picked from commit cadc893a7512ad8b5bc257062f2cebaf7ae49a55)

Conflicts:
	arch/arm/mach-msm/Kconfig
devfreq_cpubw: Add missing bits

Signed-off-by: Kostas K <mpokwsths@gmail.com>
devfreq: Add CPUBW HW monitor governor

The CPUBW HW monitor devfreq governor uses the Krait L2 PM counters to
determine the bandwidth needed by the Krait CPU subsystem. This governor
can be used in conjunction with the CPUBW devfreq device to dynamically
scale the DDR frequency based on the demand/actual usage from the Krait CPU
subsystem. Since this governor uses the Krait L2 PM counters it can
conflict with certain profiling tools.

The Krait L2 performance monitor counters have the capability to count the
no. of read/write transactions going out the master ports. They also have
the capability to raise interrupts when they overflow. This driver uses
those counters to determine the true usage of DDR from the Krait processor
subsystem and then recommends CPU DDR BW votes based on the measured values
and the following tunable parameters.

The driver provides various tunables that allow it to be tuned more in
favor of power or performance:

- io_percent: The percentage of the CPU time that can be spent waiting on
  memory I/O. Lower value is better performance and worse power.

- sample_ms: The sampling period in milliseconds. This only affects the
  sampling period when DDR use is ramping down or is increasing very slowly
  (See tolerance_percent).

- tolerance_percent: The minimum increase in DDR use, compared to previous
  sample, that will trigger an IRQ to immediately bump up the bandwidth
  vote. It's expressed as a percentage of the previous sampled DDR use.

- decay_rate: The parameter controls the rate at which the history is
  forgotten when ramping down. This is expressed as a percentage of history
  to be forgotten.  So 100% means ignore history, 0% mean never forget the
  historical max. The default 90% means forget 90% of history each time.

- guard_band_mbps: This is a margin that's added to the measured BW (and
  hence also the Bus BW votes) that's present to account for the time it
  takes to ramp up the DDR BW while the CPU continues to use the DDR.

- bw_step: All BW votes are rounded up to multiples of bw_step. The default
  value is 200 MB/s that turns out to ~25 or 12.5 MHz based on the SoC. A
  smaller value would mean more frequent bus BW changes. A higher value
  would mean less frequent BW vote updates, but also means at times an
  unnecessarily higher BW vote (due to the rounding up).

Change-Id: I88629a3e545cdca7160af8f8ca616ecc949d9947
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
(cherry picked from commit 6cad047fc7d8cf005b9ae588c3eba30e1cfeee40)
ARM: dts: msm: Add kraitbw-l2pm device for 8974

This device provides the hardware details needed by the kraitbw_l2pm
devfreq governor to measure the DDR usage from the Krait CPU subsystem and
the IRQ that's needed to react quickly to usage changes.

Change-Id: I778a36839c9b2279ab2d912715cd7eba091fe25f
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
(cherry picked from commit c5a2aad3989bedeb995ee9c8681b1c71f04f5052)
msm: clock-mdss: Toggle lock detect before checking for PLL lock

The enable sequences for the DSI PLL for MSM8226 poll a hardware
status register in order to determine whether the PLL has locked.
However, with the current sequences, it is possible that the
hardware status register would indicate a PLL lock even though the
PLL is not really locked. To avoid this, toggle the lock detect
register setting before polling for PLL lock status.

CRs-Fixed: 490476
Change-Id: I6e1357afaa6a86be9ab92095a41768873c70cf0d
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
msm: clock-8974: Change SDCC1 clock to 384MHz

Following the change of hardware configuration, SDCC1 clock frequency is
reduced to 384MHz.

CRs-fixed: 518823
Change-Id: I849b612966d286b5ee18ab4a3da4d998a696e01f
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
msm: clock-8974: Add cdccal clocks for SDCC1

In order for SDCC to config CDC calibration controller, cdccal clocks
needs to be enabled.  Add support for controlling sdcc_cdccal clocks.

Change-Id: I5959a366598612aa35f02920d5a63a251f597f9b
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
msm: clock-8974: Add support for 8974Pro aa/ab/ac variants

8974Pro aa/ab/ac have different Camera and SDCC frequencies.
Update them to match the latest clock plan.  In addition,
enable aux output of MPLL3 for Camera VFE.

Change-Id: I00835242719717de0c51f694b6976c8fe00418f1
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
msm: clock-8974: Move cdccal clocks to Pro only lookup table

SDCC cdccal clocks do not exist on v2.  Move them to 8974pro lookup
table.

Change-Id: I05ee982e53477201061cbc6bf6f2de1ae43a432f
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
msm: clock-8974: add seperate lookup table for Pro and V2

Camera MCLKs on the 8974 Pro contain MND dividers and are able to
generate all necessary sensor frequencies. Separate out the lookups
for the MCLKs and the GP clocks that were used as a substitute in
V2 and V1.

Change-Id: I99e086037955a2ed195c705a787bb904c40c7a40
Signed-off-by: Xu Han <hanxu@codeaurora.org>
msm: clock-8974: add clock entries for cti devices of remote procs

Add support for clocks required to access cti devices of remote
processors.

Change-Id: I850dc510511b924284981e3507d525fd19758eb7
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
msm: clock-8974: Change SDCC1 frequencies for MSM8974Pro AC

200MHz is replaced by 192MHz for SDCC1 on MSM8974Pro AC. Update SW
frequency table to match the new clock plan.

Change-Id: I5a3c066d0edec51a0bea5e95ce73fb0f3237539f
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
devfreq: governor_cpubw_hwmon: Remove sample_ms and fix round up of freq

devfreq already provides a sysfs interface for changing polling/sampling
period. So, there is no need for the governor to separately expose
sampling_ms. Also, sampling_ms had to be explicitly updated whenever
polling_ms was updated for the governor to function correctly. Make the
interface simpler by combining sample_ms with polling_interval control
provided by devfreq.

The rounding of freq to multiples of bw_step is unnecessary since the
devfreq device already does the rounding to the next valid level. Rounding
of AB to multiples of bw_step is still necessary since it's a vote that's
summed up and doesn't have a direct 1-to-1 mapping to frequencies.

Also update default bw_step to 190 MB/s instead of 200 MB/s to account for
the fact that MB/s to MHz conversion needs to take into account the
difference in the meaning of M (2^20 vs 10^6) between MB and MHz. Similarly
also update io_percent to 16.

Change-Id: I5fea989c647955103de3813be8eb9ec612f131bc
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
devfreq: governor_cpubw_hwmon: Fix use of decay_rate

The decay rate tunable is used to compute the current averaged bandwidth
use, but the calculated value is never used. Fix this by using the
calculated averaged bandwidth instead of the instantaneous measured
bandwidth when computing the AB and IB votes.

Change-Id: Ic0ba3ce0d98f0ec185349fe6d86c4af26f222ff2
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
msm: acpuclock-cortex: Detect bootloader cpu configuration

Detect which cpu rate is currently selected by the bootloaders during
probe. If the rate is invalid, then set the cpu rate to maximum.

Change-Id: I316d5de76133e76993a47b0d2917fd35bc5dd590
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
spi_qsd: Add vote for clock path

Currently the spi driver votes for its core clock. However, it is
possible that the core-clock's source will be off. When the source
is off, the spi core is not clocked. This patch adds voting for
the entire clock path, thus guarantee clocking to the spi core.
Voting for the path cost a few msecs. A client may choose when
to pay this overhead. By default the votes takes place in the
runtime-pm callbacks which tie to transaction requests. A client
may choose to invoke these callbacks itself whenever it likes
by directly calling the driver's runtime-pm. A third option is
to set the active_only flag in platform data which results in the
callbacks being called when the application processor power state
changes.

CRs-Fixed: 478465
Change-Id: Ib866399c0e84a875a19a0d1506d77bbe77d5fe61
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>
msm: clock-8226: Fix incorrect voltage limit value

The hw and sw frequency plan rounded the SVS frequency limit for the
vcodec clk to different values.

Change-Id: I721556cbdce7923f287eb733ccf16701ea7d3347
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>