pc: fix qemu exiting with error when -m X < 128 with old machines types

If machine doesn't support memory hotplug then staring QEMU
with initial memory less than default will make QEMU exit with
following error message:

$QEMU -m 16  -M isapc
qemu-system-i386: "-memory 'slots|maxmem'" is not supported by: isapc

Set maxram_size to initial memory value before parsing
'maxmem' option allows to keep maxmem in sync with initial
memory size if no maxmem option was specified.

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
CC: Bruce Rogers <brogers@suse.com>
Merge branch 'master' of git://git.qemu.org/qemu
Merge branch 'master' of git://git.qemu.org/qemu
Merge branch 'master' of git://git.qemu.org/qemu
Merge branch 'master' of git://git.qemu.org/qemu
Merge branch 'master' of git://git.qemu.org/qemu
Merge branch 'master' of git://git.qemu.org/qemu
Merge branch 'master' of git://git.qemu.org/qemu
Merge branch 'master' of git://git.qemu.org/qemu
Merge branch 'master' of git://git.qemu.org/qemu
Merge branch 'master' of git://git.qemu.org/qemu
Merge branch 'master' of git://git.qemu.org/qemu
Merge branch 'master' of git://git.qemu.org/qemu
target-mips: Correct the handling of register #72 on writes

Fix an off-by-one error in `mips_cpu_gdb_write_register' for register
matching how `mips_cpu_gdb_read_register' handles it.  This register
slot is a fake anyway, there's nothing in hardware that corresponds to
it.

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
target-mips: Make CP1.FIR read-only here too

CP1.FIR is read-only in hardware so gdbstub must respect it.  We already
respect it for CTC1 instructions, so do it here too.

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
target-mips: Add 5KEc and 5KEf MIPS64r2 processors

Add the 5KEc and 5KEf processors from MIPS Technologies that are the
original implementation of the MIPS64r2 ISA.

Silicon for these processors has never been taped out and no soft cores
were released even.  They do exist though, a CP0.PRId value has been
assigned and experimental RTLs produced at the time the MIPS64r2 ISA has
been finalized.  The settings introduced here faithfully reproduce that
hardware.

As far the implementation goes these processors are the same as the 5Kc
and the 5Kf CPUs respectively, except implementing the MIPS64r2 rather
than the original MIPS64 instruction set.  There must have been some
updates to the CP0 architecture as mandated by the ISA, such as the
addition of the EBase register, although I am not sure about the exact
details, no documentation has ever been produced for these processors.
The remaining parts of the microarchitecture, in particular the
pipeline, stayed unchanged.  Or to put it another way, the difference
between a 5K and a 5KE CPU corresponds to one between a 4K and a 4KE
CPU, except for the 64-bit rather than 32-bit ISA.

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
target-mips: Make CP0.Config4 and CP0.Config5 registers signed

Make the data type used for the CP0.Config4 and CP0.Config5 registers
and their mask signed, for consistency with the remaining 32-bit CP0
registers, like CP0.Config0, etc.

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
target-mips: Add M14K and M14Kc MIPS32r2 microMIPS processors

Add the M14K and M14Kc processors from MIPS Technologies that are the
original implementation of the microMIPS ISA.  They are dual instruction
set processors, implementing both the microMIPS and the standard MIPSr32
ISA.

These processors correspond to the M4K and 4KEc CPUs respectively,
except with support for the microMIPS instruction set added, support for
the MCU ASE added and two extra interrupt lines, making a total of 8
hardware interrupts plus 2 software interrupts.  The remaining parts of
the microarchitecture, in particular the pipeline, stayed unchanged.

The presence of the microMIPS ASE is is reflected in the configuration
added.  We currently have no support for the MCU ASE, including in
particular the ACLR, ASET and IRET instructions in either encoding, and
we have no support for the extra interrupt lines, including bits in
CP0.Status and CP0.Cause registers, so these features are not marked,
making our support diverge from real hardware.

Signed-off-by: Sandra Loosemore <sandra@codesourcery.com>
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
target-mips: Enable vectored interrupt support for the 74Kf CPU

Enable vectored interrupt support for the 74Kf CPU, reflecting hardware.

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
target-mips: Fix formatting in `decode_extended_mips16_opc'

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>