Created a Ram-module with decoupled Deq/Enq IO
Rename w-argument to dataWidth
Merge branch 'master' into ram-tile
First draft of RamTile.
The module wires all but the *last* RouterPort with the internal router-module. The last RouterPort is wired up with the internal Ram-module.
The rest of the ports is exposed through the RamTileIO-bundle
Merge branch 'master' into ram-tile
Create update-function that constructs packets using UInts instead of int-values
Make the ram sequential
Use PacketData.update instead of create, which is more suited for generating packets in HW instead of tests
Two cycle-test that sends a packet to the tiles east-port and writes the data to ram