vc4: Shove some depth comparison bits down to where they're used.
vc4: Don't try to do stores to buffers that aren't bound.

The code was kind of mixed up what buffers were getting stored in the case
that a resolve bit was unset (which are set based on the GL state at draw
time) and the buffer wasn't actually bound.  In particular, depth-only
rendering would store the color buffer contents, which happen to be
pointing at the depth buffer.

Thanks to clearing out the resolve bits for things we really can't
resolve, now I can drop the safety checks for buffer presence around the
actual stores.

Fixes 42 piglit tests.
driconf: Synchronize po files

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
driconf: Update Spanish translation

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
driconf: Correct and update Catalan translation

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
i965: Delete intel_chipset.h.

Unused; it was replaced by include/pci_ids/i965_pci_ids.h long ago.

Acked-by: Matt Turner <mattst88@gmail.com>
st/xa: Fix regression in xa_yuv_planar_blit()

Commit "st/xa: scissor to help tilers" broke xa_yuv_planar_blit() and vmwgfx
textured video. Fix this by implementing scissors also in the yuv draw path.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Cc: Rob Clark <robclark@freedesktop.org>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
ilo: use dynamic bo for rectlist vertices

The size is always 24 bytes.  We can upload them to the dynamic buffer.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
ilo: precalculate aligned depth buffer size

To replace the hacky zs_align_surface().

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
ilo: add a pass to finalize ilo_ve_state

Add finalize_vertex_elements() to finalize ilo_ve_state.  This fixes a
potential issue with URB entry allocation for VS and move the complexity of
gen6_3DSTATE_VERTEX_ELEMENTS() to the new function.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
ilo: fix format of edge flag pointer

The VE format of edge flag pointers was changed in
780ce576bb1781f027797039693b98253ee4813e.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
radeonsi: Fix tiling mode index for stencil resources

We are currently only dealing with depth-only or stencil-only resources
here, not with resources having both depth and stencil[0]. In both cases,
the tiling mode index is in the tile_mode field, not in the
stencil_tile_mode field.

[0] Add an assertion for that.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
radeonsi: Fix si_dma_copy(_tile) for compressed formats

Fixes GPUVM faults when running the piglit test "getteximage-formats
init-by-rendering" with R600_DEBUG=forcedma on SI.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
radeonsi: Catch more cases that can't be handled by si_dma_copy_buffer/tile

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
radeonsi: Pass the slice size to si_dma_copy_buffer

Otherwise some parts of tiled slices can be missed.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
i965/fs: Manually generate the meta fast-clear shader

Previously, we were generating the fast-clear shader from GLSL.  The
problem is that fast clears require that we use a replicated write rather
than a regular write instruction.  In order to get this we had a
complicated and somewhat fragile optimization pass that looked for places
where we can use a replicated write and used it.  Since replicated writes
have a lot of restrictions, we only ever use them for fast-clear
operations.

This commit replaces the optimization pass with a function that just
generates the shader we want.  This is a) less code, b) less fragile than
the optimization pass, and c) generates a more efficient shader.

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
i965/fs_live_variables: Use var_from_vgrf insead of repeating the calculation

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965/fs: Rewrite fs_visitor::split_virtual_grfs

The original vgrf splitting code was written with the assumption that vgrfs
came in two types: those that can be split into single registers and those
that can't be split at all It was very conservative and bailed as soon as
more than one element of a register was read or written.  This won't work
once we start allowing a regular MOV or ADD operation to operate on
multiple registers.  This rewrite allows for the case where a vgrf of size
5 may appropriately be split in to one register of size 1 and two registers
of size 2.

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
i965/fs: fix a comment in compact_virtual_grfs

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965/fs: Use offset a lot more places

We have this wonderful offset() function for advancing registers, but we're
not using it.  Using offset() allows us to do some sanity checking and
avoid manually touching fs_reg::reg_offset.  In a few commits, we will make
offset do even more nifty things for us.

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>