Update to distinguish from release
efm32wg-stk3800: add board

Basic clone of efm32gg-stk3700; change device information, switch to M4
with FPU, add FPUEH vector entry.
efm32gg990f1024: remove redundant architecture line

Architecture is set at the efm32gg level.
efm32zg-stk3200: add board

First Cortex-M0+ architecture.  Has USART and LEUART but no UART; vector
table is quite diminished.
core: work around lack of cycle counter on M0+

Make the enable/disable functions no-ops; provide a loop-based hack so
use of this for crude delays still functions.
gcc_arm.ld: remove GROUP command

This looked odd before since one might be using nano (libc_s.a) and not
linking newlib's conception of nosys.  Here's ek-tm4c123gxl nop with the
original:

   text    data     bss     dec     hex filename
   1920    1080      28    3028     bd4 app.axf

And here it is with the GROUP command removed:

   text    data     bss     dec     hex filename
   1324     112      28    1464     5b8 app.axf

github: fixes #4
bootstrap/stdio: restore default WITH_NANO use

Turns out the problems with buffering were due to issue #4, and not
newlib-nano itself.
Makefile.common: clean up newlib/toolchain/library stuff

Specifically note that it would be unwise to let code know whether it's
being built for newlib-nano, since it may or may not be linked with
newlib-nano.
devinfo: add example

This just dumps everything that the device can introspect onto the
console; memory sizes, product revision, etc.
Makefile.common: add -ggdb to OPT_LDFLAGS

This doesn't actually make any difference, since -ggdb was in the object
files and linking doesn't remove that data, but it's still good to make
the expectations clear.
efm32: provide SWO initialization function

This function enables trace and debug port functionality used by the
energyAware Profiler.
core: add support for bitband SRAM and PERIPH access

Only supported on M3/M4 devices, not M0+.  Not useful for setting
multiple bits simultaneously.  Useful for manipulating individual
peripheral register bits when the bit and the register address are
compile-time constants, and when setting flags in an event record while
interrupts are enabled.

Note that peripheral registers are always accessed as 32-bit objects,
while SRAM objects may be accessed as smaller entities.
efm32: add utility function to set value of packed nybble

Easier than getting the masks and shifts and word offsets right all
over.

Note that this required moving the toolchain helper macros up so they're
visible when processing the device-specific header.
core: implement sleep-mode macros

Specifically this describes the expected semantics, which does not
include leaving SLEEPDEEP set in SCR as is done by EMU_EnterEM2() on
EFM32.
uart: add flush function
cleanup: correct documentation macro
fdops: remove fcntl(2) support

The newlib build flags for ARM exclude HAVE_FCNTL, so newlib provides a
strong definition of this function that returns -1/ENOSYS, overriding
the definition here.  Since fcntl() operations are the purview of libc,
we'll remove the override.  It becomes more likely that ioctl will be
needed, then.

This also resolves the question of whether O_NONBLOCK, O_ASYNC, or
O_DIRECT might be usable: no.
uart: rework transmission architecture

In support of low-energy use we want the application to have more
control over what to do when resources are unavailable.

The UART write operation will no longer ever block or enable interrupts
in order to transmit something.  The bridge to newlib will do this if
necessary to satisfy newlib's requirements.  Interrupts are now disabled
during transmit only to protect tx_fifo_ni_ and tx_state_.  UART FIFOs
are now optional, eliminating space overhead if programmed IO or DMA are
intended to be used.  FIFOs if present are accessed only when interrupts
are disabled.
leuart: disable interrupts when deconfiguring
periph/uart example: demonstrate testing for non-standard uart