Changed target part to LFE5UM-45F-6BG381C

Changed to the part that will be used on Titan rev C (and likely from
that rev on).
Added the DDR3 core and instantiation.

This is a rough implementation. The pinout does not yet match Titan,
the user (internal) interface is tied-off, and DQS and CK0 are
single-ended rather than differential.
Added ddr3_x16 to README
Corrected syntax errors
Updated design to get the DDR3 to route

1) Changed the clock input to the DDR3 core from the sys clock output
of the PCIe core to the oscillator (using the PCIe output clock caused
a routing error)
2) Removed the 1.5V bank voltage setting for the DDR3 pins. This seems
wrong, but changing it resolved the route error.
Assigned DDR3 partially according the Titan-B
Moved DDR3 pin settings from Clarity to LPC file
Changed DDR3 CK0 and DQS0/1 to SSTL15D

This sets the clock and data strobe nets to be differential pairs (and
was validated in the Pin Report in Diamond)
Merge pull request #1 from jsloan256/ddr

Add stubbed DDR3 core and convert to the ECP5 45
Merge pull request #2 from c-e-s/ddr

Pull the DDR3 additions into the master branch