mesa: s/INLINE/inline/

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
meta: s/INLINE/inline/

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
xlib: s/INLINE/inline/

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
osmesa: s/INLINE/inline/

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
swrast: s/INLINE/inline/

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
state_tracker: Fix bug in conditional discards with native ints.

A bool is 0 or ~0, and KILL_IF takes a float arg that's <0 for discard or
>= 0 for not.  By negating it, we ended up doing a floating point subtract
of (0 - ~0), which ended up as an inf.  To make this actually work, we
need to convert the bool to a float.

Reviewed-by: Brian Paul <brianp@vmware.com>
vc4: Stop being so clever in CMP handling.

This kind of cleverness should be in a general merging-of-ADD-and-MUL
instruction scheduler, rather than individual opcodes.
vc4: Expose compares at a lower level in QIR.

Before, we had some special opcodes like CMP and SNE that emitted multiple
instructions.  Now, we reduce those operations significantly, giving
optimization more to look at for reducing redundant operations.

The downside is that QOP_SF is pretty special -- we're going to have to
track it separately when we're doing instruction scheduling, and we want
to peephole it into the instruction generating the destination write in
most cases (and not allocate the destination reg, probably.  Unless it's
used for some other purpose, as well).
vc4: Switch to using native integers.

There were troubles with bools without using native integers
(st_glsl_to_tgsi seemed to think bool true was 1.0f sometimes, when as a
uniform it's stored as ~0), and since I've got native integers other than
divide, I might as well just support them.
vc4: Add a CSE optimization pass.

Debugging a regression in discard support was just too full of duplicate
instructions, so I decided to remove them instead of re-analyzing each of
them as I dumped their outputs in simulation.
i965/fs: Add init function to fs_visitor

This common init routine can be used by constructors for multiple program
types.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965/fs: Use stage_prog_data instead of prog_data->base in fs_visitor

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965/fs: Use prog rather than fp->Base in fs_visitor

Reduce fs_visitor's dependence on gl_fragment_program.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
vc4: Merge qcompile and tgsi_to_qir

The split between these two didn't make much sense.  I'm going to want the
chance to look at uniform contents in optimization passes, and the QPU
emit I think is going to end up rewriting the uniforms stream.
freedreno/ir3: bit of debug

Make it easier to figure out which compiler stage failed.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
freedreno/ir3: fix error in bail logic

all_delayed will also be true if we didn't attempt to schedule anything
due to no more instructions using current addr/pred.  We rely on coming
in to block_sched_undelayed() to detect and clean up when there are no
more uses of the current addr/pred, which isn't necessarily an error.

This fixes a regression introduced in b823abed.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
freedreno/ir3: fix constlen with relative addressing

We can't rely on the value from the assembler if relative addressing is
used.  So instead use the max of declared-consts (which does not include
compiler immediates) and what we get from the assembler (which does).

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Revert 5 i965 patches: 8e27a4d2, 373143ed, c5bdf9be, 6f56e142, 88e3d404

Reverts
* "i965: Modify state upload to allow 2 different sets of state atoms."
   8e27a4d2b3e4e74e9a77446bce49607433d86be3
* "i965: Modify dirty bit handling to support 2 pipelines."
   373143ed9187c4d4ce1e3c486b5dd0880d18ec8b
* "i965: Create a macro for checking a dirty bit."
   c5bdf9be1eca190417998d548fd140c1eca37a54
   Conflicts:
	src/mesa/drivers/dri/i965/brw_context.h
* "i965: Create a macro for setting all dirty bits."
   6f56e1424d923fd80c84090fbf4506c9eaaffea1
   Conflicts:
	src/mesa/drivers/dri/i965/brw_blorp.cpp
	src/mesa/drivers/dri/i965/brw_state_cache.c
	src/mesa/drivers/dri/i965/brw_state_upload.c
* "i965: Create a macro for setting a dirty bit."
   88e3d404dad009d8cff5124cf8acee7daeaceb64

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
clover: Use conversion operator to initialize build log from compat::string.

Fixes binary garbage in the compilation logs caused by
compat::string::c_str() not being null-terminated (which is a bug on
its own that will be fixed in another commit).

Reported-by: EdB <edb+mesa@sigluy.net>
clover/util: Have compat::vector track separate size and capacity.

In order to make the behaviour of resize() and reserve() closer to the
standard.

Reported-by: EdB <edb+mesa@sigluy.net>