ARM: dts: msm: tuning 8x12 skuab hx8389b panel with gamma 2.2

Panel's gamma curve should be standard 2.2 or 2.6 curve.
Tuning 8x12 skuab hx8389b panel to standard 2.2 curve.

Change-Id: I9aad5ba006bb75e6650ae53933ea88acc206e4c5
Signed-off-by: Shuo Yan <shuoy@codeaurora.org>

Conflicts:
	arch/arm/boot/dts/dsi-panel-hx8389b-qhd-video.dtsi
ARM: dts: msm: adjust 8x12 skuab HX8389B mipi clock to 240.42MHZ

Currently, mipi clocking running at 276MHZ which affects GSM signal
on 8x12 SKUAB Himax8389b panel. Changing the mipi clock frequency
to 240.42MHZ to avoid RF interference.

Change-Id: I3fb3d3d3303464056cc71f48b6356698195c4b55
Signed-off-by: Shuo Yan <shuoy@codeaurora.org>
msm: lpm_levels: Support for RPM PC on all cores

When more than one core is online, the current model prevent entering
idle power collapse on all cores and the deepest sleep mode that a
cpu could enter is standalone power collapse. To achieve better power
savings when several cores are online all the time, it is important for
multiple cores to enter a deeper system sleep state by configuring L2
and RPM.

Each core entering the deepest sleep mode increments a counter. The
last core to enter the deepest sleep mode will acquire a lock and will
be responsible for configuring the system low power mode.  cpus. The
last core going down will configure the system wide resources with the
lock held. If a core were to wakeup during this time, it would have to
wait for the lock to be released before it can continue to resume. The
last core releases the lock after configuring the system resources at
which point, the core that resumed from power collapse would reset the
system resources before continuing to run to ensure that the shared
resources are programmed for a safe state.

With this change the idle PC becomes more of a soft state where each
core identifies that its safe to enter a system sleep state. The
decision to enter a system sleep mode is based on the next wakeup event
across all cores. With not all cores encoutering latency associated with
system sleep modes, the residency of idle PC mode will be lower than
what it has been previously acheived. However, the residency of the
system sleep states should be unaffected.

Each core as its power collapsed disables the HFPLL and switches to
GFPLL in the event of a power collapse. During this time, each cores
removes its vote to keep L2 enabled. To ensure that there are enough
votes for keep L2 on, set the number of L2 votes to number of online
cpus in cpufreq.c

Change-Id: If6a8e181bdb9c7bae8066fb804de13caa48bad3b
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>

Conflicts:
	arch/arm/boot/dts/msm8226-v1-pm.dtsi
	arch/arm/boot/dts/msm8226-v2-pm.dtsi
	arch/arm/boot/dts/msm8610-v1-pm.dtsi
	arch/arm/boot/dts/msm8610-v2-pm.dtsi
	arch/arm/mach-msm/lpm_levels.c
ARM: dts: msm: Add L2 perf monitor interrupts to bypass list

Corrected L2 perf monitor interrupt name to APCC_qgicL2PerfMonIrptReq in the list.

The L2 perf monitor interrupts can only come when the CPU subsystem is active
and powered on. So, put it in the bypass list so that XO shutdown is not
blocked to allow processing this interrupt when the CPU subsystem is power
collapsed.

Change-Id: I1ae4dc9e800ac2d7188d45ef7634530d93049340
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
Signed-off-by: Girish Ghongdemath <girishsg@codeaurora.org>
msm: mdss: Handle solid fill call with width one correctly

If userspace calls solid fill with width one, even alignment in
driver will make it zero and this will result in page fault.
Handle this case in driver by making this width two rather than
zero if it is not crossing the buffer boundary.

Change-Id: I84c9ed7e029cb98f4fb7c5d92e09fd2a54d74662
Signed-off-by: Shivaraj Shetty <shivaraj@codeaurora.org>

Conflicts:
	drivers/video/msm/mdss/mdp3_ppp.c
msm: mdss: Verify histogram size before sending to user

Add check to DSPP histograms to verify that the number of pixels
collected
is the same as the resolution of the region being processed.

Change-Id: I21acd1b4a25d06391c853e7495ca3fb3bb0ffef4
Signed-off-by: Carl Vanderlip <carlv@codeaurora.org>
Signed-off-by: Ping Li <quicpingli@codeaurora.org>

Conflicts:
	drivers/video/msm/mdss/mdss_mdp_pp.c
mmc: host: Use sentinels for devicetree match tables

Use sentinels as the path terminator for device match table
in drivers msm_sdcc.c and sdhci-msm.c. Without this, of_dev_lookup()
may run off the end of the array looking for bogus data.

CRs-Fixed: 582113
Change-Id: I069d3e058cea9f1bf74d48e7f7e83465ca981017
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>

Conflicts:
	drivers/mmc/host/sdhci-msm.c
msm: mdss: esd recovery support for 8x10 targets

This patch adds kernel side support for esd recovery for mdp3
targets. This patch adds the functionality to driver to check
the panel status periodicaly and send event to HAL if it detects
that panel has gone bad.

Change-Id: I901e2908beb5de3f557da7d75cca876a40532efe
Signed-off-by: Shivaraj Shetty <shivaraj@codeaurora.org>

Conflicts:
	drivers/video/msm/mdss/Makefile
	drivers/video/msm/mdss/dsi_host_v2.c
msm: mdss: esd recovery support in command mode for 8x10 targets

This patch extends support for esd recovery for command mode panels
on 8x10 targets.

Change-Id: Icf289918e46f5c975d459355823ff62916cb66d1
Signed-off-by: Shivaraj Shetty <shivaraj@codeaurora.org>
msm: mdss: Add an extra write of zero to clear dsi-ack-err bit

In addition to writing 1 to clear dsi-ack-err bit, an extra write
of 0 is also needed to clear error bit completely.

CRs-fixed: 574066
Change-Id: Ib9df9fe5f993605372ced8766874fa00538f505a
Signed-off-by: Shivaraj Shetty <shivaraj@codeaurora.org>
msm: mdss: Update the dma stride value on mdp3

The frame buffer is allocated from user space. And it may have some
special alignment requirement. Rather than assuming the alignment in
the driver, this change is to use the value passed in from the
user space to configure the dma stride register.

CRs-fixed: 582796
Change-Id: Ic3884ee0a530ed1ab83b6df26ba180fd21257ae0
Signed-off-by: Shivaraj Shetty <shivaraj@codeaurora.org>
mdss: Fix null point dereference in mdss_mdp_pp_init

Fixed null point dereference in case of memory allocation
failure in mdss_mdp_pp_init.

Change-Id: I3593a583da355915b731ac30b1f38aaa010eba85
Signed-off-by: Krishna Chaitanya Parimi<cparimi@codeaurora.org>
arm: dts: Fix incorrectly named cpu mode.

The standalone pc mode was incorrectly marked as spc instead of
standalone-pc

Change-Id: Ia6485ff20a7d123f76d1149c16611d5f526d3c3b
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
ARM: dts: msm: Optimize DDR frequency

Experiments have shown that it is more efficient to run DDR at 200 MHz
when the cpu is at 600 MHz.

Change-Id: Iba12ffe484d8057dedae81f3b8e1b6df5a4460be
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>

Conflicts:
	arch/arm/boot/dts/msm8226.dtsi
ARM: dts: msm: Update bus frequency requests for 8226

Reduce the bus frequency used for 787.2 MHz to improve power.

CRs-Fixed: 549699
Change-Id: Ia87ccf306b153c4798b2a890c76086bd014ef122
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
ARM: dts: msm: Correct maximum cpu frequency

Use the correct value for the maximum cpu speed.

CR's-Fixed: 585994
Change-Id: I38ae7a9d188e2a8d96a5ed7c005eae79f0fe07a4
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>

Conflicts:
	arch/arm/boot/dts/msm8226-v2.dtsi
msm: mdss: Add six zone LUT size as PAv2 parameter

Added six zone LUT size as a parameter to PAv2 in order for the size to be
specified by the user. This size is sanitized based on the required LUT
size.

Change-Id: Iaf1b418ce1a3ec4b5013b1192c7f3b7de5827e3d
Signed-off-by: Benet Clark <benetc@codeaurora.org>
msm: mdss: Fix error in BL linearity inverse LUT check

Associate the maximum index for the BL linearity inverse LUT with the
table size and not the maximum backlight value. The maximum backlight
value can cause an out of bounds index for the BL linearity inverse LUT.

Change-Id: I35fb276f8f1cc6be3be158fa25e6442be438cbf0
Signed-off-by: Benet Clark <benetc@codeaurora.org>
msm: mdss: Sanitize read of panel properties

Check panel property's values properly before operating on
them.

CRs-Fixed: 562887
Change-Id: I26ce51e8b3a8e9328e7b6370b9c56d67fcdd1901
Signed-off-by: Mayank Chopra <makchopra@codeaurora.org>

Conflicts:
	drivers/video/msm/mdss/mdss_dsi_panel.c
msm: mdss: enable vsync event during continuous splash

Currently when continuous splash screen is enabled the vsync
event reports are delayed until first frame update. This blocks
boot animation. To fix this issue, after user space enables
vsync through vsync_ctrl, mdp driver will start sending vsync
events.

CRs-fixed: 567649
Change-Id: Ifb35e3479805e595d950ab7c38c26de201aa2d16
Signed-off-by: Ray Zhang <rayzhang@codeaurora.org>

Conflicts:
	drivers/video/msm/mdss/mdss_mdp_ctl.c