Fixed shift register issues

Also made it simpler in the process. yay?
Fixed the shift register

It works now! The shift register that is. Correct endianiness was the
fix.
Fixed timing bug on ram_address

wasn't holding seen_header long enough.
bugfixing

narrowed it down to FIFO issue
and it's back to the FIFO EMPTY issue

let's get it done? And by us I mean me.
Code working except for double packets/long delays?

Bugfix 50MHz presumablyu
changing width of enum

asdlkfjasl;dkfj
tweaked minor errors
fucked up commit

this one is no good