Now using the XESS Library for the fast clk
use XESS.ClkgenPckg.all;     -- For the clock generator module.
Next will be adding the jpeg to the top_level_mod
The HostIo function is not implement but getting ready
use XESS.HostIoPckg.all;     -- For the FPGA<=>PC transfer link module.

The Sdram function is not implement but getting ready

use XESS.SdramCntlPckg.all;  -- For the SDRAM controller module.