target-arm: A64: Implement PMULL instruction

Implement the PMULL instruction; this is the last unimplemented insn
in the three-reg-diff group.

Note that PMULL with size 3 is considered part of the AES part
of the crypto extensions (see the ID_AA64ISAR0_EL1 register definition
in the v8 ARM ARM), so it isn't necessary to burn an extra feature
bit on it, even though we're using more feature bits than a single
"crypto extension present/not present" toggle.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: A64: Fix bug in add_sub_ext handling of rn

rn == 31 always means SP (not XZR) whether an add_sub_ext
instruction is setting the flags or not; only rd has behaviour
dependent on whether we are setting flags.

Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: A64: Add last AdvSIMD Integer to FP ops

This adds the remaining [US]CVTF operations to the SIMD
shift-immediate, scalar-shift-immediate, two-reg-misc and
scalar-two-reg-misc groups of opcodes.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
[PMM: added scalar 2-misc and scalar-shift-imm encodings]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: A64: Add FSQRT to C3.6.17 (two misc)

Implement FSQRT in the two-reg-misc category.
GCC uses this instruction form.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: A64: Add remaining CLS/Z vector ops

Implement the CLS, CLZ operations in the 2-reg-misc category.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: A64: Saturating and narrowing shift ops

This implements the remaining [US][Q][R]SHR[U][N][2] opcodes, which are
saturating and narrowing shift right operations. These are used in
things like libav. Note signed shifts can have an "unsigned" saturating
narrow operation which will floor negative values.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
[PMM: Added the scalar encodings, style tweaks]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP

Implement the SADDLP, UADDLP, SADALP and UADALP instructions
in the SIMD 2-reg misc category.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: A64: Implement SHLL, SHLL2

Implement the SHLL and SHLL2 instructions from the 2-reg-misc
category.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions

Implement the floating-point-to-integer conversion instructions
FCVT[NMAPZ][SU] in the 2-reg-misc and scalar-2-reg-misc
categories.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: A64: Implement FCVTN

Implement FCVTN (narrowing fp-to-fp conversions) from the SIMD
2-reg-misc category.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: A64: Implement FCVTL

Implement FCVTL, the only instruction in the 2-reg-misc group
which widens from size to 2*size elements.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: A64: List unsupported shift-imm opcodes

Add the remaining unsupported opcodes to the decode switches
for the shift-imm and scalar shift-imm categories so we can
see what is still to be implemented.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: A64: Add FRECPX (reciprocal exponent)

These are fairly simple exponent only estimation functions using helpers.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: A64: Implement SRI

Implement SRI (shift right and insert).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: A64: Implement FRINT*

Implement the FRINT* round-to-integral operations from
the 2-reg-misc category.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoder

The ARM A64 decoder's worst case number of TCG ops per instruction
is 266 (for insn 0x4c800000, a post-indexed ST4 multiple-structures
store). Raise the MAX_OP_PER_INSTR define accordingly.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHL

Implement the saturating left shift instructions SQSHL, SQSHLU
and UQSHL for the scalar-shift-imm and shift-imm categories.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categories

Implement FCVTZS and FCVTZU in the shift-imm and scalar-shift-imm
categories; this completes the implementation of those two groups.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
softfloat: export squash_input_denormal functions

I need these available outside of softfloat for some of the reciprocal
processing in aarch64 helper functions.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: A64: AdvSIMD reciprocal estimates

The actual reciprocal function is shared with the NEON code. The include
URECPE and FRECPE instructions in both scalar and vector forms.
However in the v8 world there are more steps applied to ensure correct
handling of de-normal conditions. I've added these to the existing arm32
NEON helpers although it doesn't affect normal arm32 operation. I've
also modified the calling conventions for the helpers to pass the fpst
directly and mark the helpers as TCG_CALL_NO_RWG.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>