root bug corrected
Merge pull request #21 from hansiglaser/master

beautified write_intersynth, enabled multiple "-map" for the extract pass
Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys
Added first presentation slides
Progress on presentation
Progress on presentation
Renamed manual/FILES_* directories
presentation progress
Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal)
Added read_verilog -icells option
Updated ABC to hg rev e6b09e1
Added test comments to techlibs/cmos/cmos_cells.lib
Added -h command line option
Tiny change in example script in README
presentation progress
presentation progress
Added yosys -H for command list
Bugfix in name resolution with generate blocks
presentation progress
More changes to techlibs/common/simlib.v for LEC