Revert "-fs Backport Flash-Friendly FileSystems (f2fs) --nowcomputing"

This reverts commit 5eaf4a24d69cc31488983f18832cbfa8b659d766.
lto compression 7
update optimizations
disable frame pointer for more performance
cleaning up a lil
Revert "OMAPDSS: DSS: Relax L3 bus bandwidth constraint"

This reverts commit 1f5051dd8a37d192c3b17da1edc99a529477efad.
Revert "OMAP4: OMAPDSS: Request higher bandwidth for 1080p FB"

This reverts commit 17f7b9c8533355f97422fad918bc331200f97106.
Revert "OMAP4: clock: Extend L3 clock dependencies to cover 4470"

This reverts commit 3422f831ab6d689ef495c4dcbd6913fadc0b278d.
Revert "Cross Memory Attach"

This reverts commit 9392ec56256a3f5ae7ba5fd94fb974cdcd4cf8a0.
tune row
update target residency for c-stats<faux123
wtf r u
derp
drivers/staging/android: backport hammerhead lowmemorykiller
All commits up to:
	android: lowmemorykiller: add lmk parameters tunning code.

backport & squash by boype
tune lmk
OMAP4: do not force workarounds for errata fixed in 4460

Signed-off-by: Mans Rullgard <mans.rullgard at linaro.org>
Enable PL310 double linefill for Tuna board

Double linefill was disabled because of single cache line
corruption in first revisions of OMAP 4460. On Tuna board,
after extensive testing, no cache corruption cases were
observed.

Benchmarks (RgBandwidth, Antutu) show up to 45% performance
gains in memory bandwidth tests.

RgBandwidth (Threads: Auto, Test: Misc)

     Single Linefill   Double Linefill

Copy   1403.0 MB/s  ->  1826.6 MB/s
Scale  1386.8 MB/s  ->  1672.2 MB/s
Add    1227.7 MB/s  ->  1778.9 MB/s
Triad  1225.3 MB/s  ->  1746.2 MB/s
Tuna: set PL310 cache controller prefetch offset to 3

Now that double linefill is enabled the PL310 prefetch
offset needs re-evaluation. Benchmarks show that value
of 3 (or 4, close second) is the optimal value.

Performance gains in memory bandwidth tests up to 9%.

RgBandwidth (Threads: Auto, Test: Misc)

Copy   1826.6 MB/s  ->  1915.8 MB/s
Scale  1672.2 MB/s  ->  1812.7 MB/s
Add    1778.9 MB/s  ->  1905.3 MB/s
Triad  1746.2 MB/s  ->  1844.7 MS/s
Enable SCU Speculative linefills

By enabling SCU Speculative linefills in the SCU Control
Register, the  L2 cache access latency seems tp be reduced
a bit with an overall ~1.5% improvement.
tuna: Enable Cortex A9 optimizations

Enable Zero fills and tune speculative SCU line feeds for tuna board