hp/pavilion_m6_1035dx: Map USB and PWRB PME sources to GPE 11

Hudson ASL files assume the USB power envent notifications are mapped
to GPE 0xb. Since that GPE is not used on this board, map these events
to GPE11. This GPE is already handles in ACPI via Method(_L0B). We
adjust this method to also notify the XHCI controller at PCI 10:0.

Change-Id: If33dd4bb5830820227f7c8b34594886cfae37282
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
hp/pavilion_m6_1035dx: Do not re-init EC and SMI on S3 resume

It's not needed, and puts the EC back into APM mode. The EC does not
shut down during S3 sleep, so we don't need to re-initialize it.
SMI triggers don't need to be set up again, as that resets their state
and re-enables shutdown on lid close.

Change-Id: I2c06df140f63427dac32ae095d29e68f64135358
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
hp/pavilion_m6_1035dx: Map PCIE PME sources to GPE 0x18

The PCIE PME pin from the APU is connected to GEVENT8, but the
northbridge's ASL hardcodes this to GPE 0x18. Adjust the SCI map
accordingly.

Change-Id: Ie395e62919f6e97ef9bcc45c736f9debf4e09ba0
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
southbridge/hudson: Disable USB controllers if devicetree says so

Change-Id: I009a01d3324d48d2eeda87d74c8e3e7c27958ee2
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
usbdebug: Reduce bus reset delays

According to EHCI specification, host controller software stops
the USB Reset condition by writing PORT_RESET=0. Software then
poll-waits this bit until controller hardware has completed USB
Reset sequence and read returns with PORT_RESET==0.

Change-Id: I6033c4d904c2af9eb16f5f3c1eb825776648cc1d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
usbdebug: Add optional quirk for old DIY debug part

Not sure what this is about. Required for FX2.

Change-Id: I86878f8f570911ed1ed3ec844c232ac91e934072
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
vendorcode/amd/agesa/fam15tn: Clean #includes in public headers

Right now, coreboot code using AGESA headers can only build if all the
AGESA path are given to the compiler via the "-I" option. This is sub-
optimal, as it requires us to have every AGESA source directory
specified as a compiler include path. This pollutes our global include
paths.

We restrict the compiler include paths to only allow "AGESA_ROOT/" and
"AGESA_ROOT/Include". We then modify the AGESA headers to specify
non-local include files relative to "AGESA_ROOT/Include".

We use the convention that includes relative to the directory of the
header are included as "path/to/header.h", while includes relative to
AGESA_ROOT are included as <path/to/header.h>.

This change allows building coreboot code based on AGESA with the
limited subset of include paths, but does not allow AGESA itself to
build with this restricted subset.

Change-Id: I31102273c8caa8d6b1d80774bfd35711825bec03
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
NOTFORMERGE: Add tons of ACPI debug info

Change-Id: I2475ba04a5258f9d8af9b987a461ec2d5ab60135
NEVERMERGE: Temporarily disable USB ctrl

Change-Id: Ie15fc912ed74b2a49ec005cc8145e88cc0e628a3
NEVERMERGE: Add SMI debugger

Change-Id: I7aff8a976d95c32b24a91940faefe4fd18a713ce
NOTFORMERGE: Hack in usbdebug to SMM

Change-Id: I2fba3f665ff0a18c9edbd726aad7a7123a42a620