Fix race condition where a L1 miss will be sent twice if the request is sent the same cycle a collided miss occurs

Some other cleanup
Fix bug where the same data was cached in multiple icache ways

The bitmap that indicated which threads could be fetched needed to be ored together.
It was treated as a single signal, which ended up truncating high bits.  As a result,
tag memory wouldn't be read, but the next stage would still compare and trigger a miss
in cases where the data was cached.  It would then be reloaded into another way.
Add a few more assertions