Improved ioreg macro

This is the beginning of a syntax extension to generate register definitions with type-safe bitfields and enable opportunistic use of bitbanding.

A register set is defined in a domain-specific language parsed by the `ioregs!` macro. There are three primitives in this language,

  * *registers* are defined by a name, an offset from the beginning of
    the containing group, and a type. Register types include group of registers and primitive bitfield types ( `reg32`, `reg16`, `reg8`)
  * *fields* are a range of bits within a bitfield, identified by a
    name and a type (either implicitly `uint` or `bool`, or an syntactically explicit `enum`)

Register and field types can both be arrays.

For example, consider [this](https://gist.github.com/bgamari/071e50b185278f56dc78#file-example-registers-txt) register set. This would be translated to the proposed DSL as follows,

```rust
ioregs!(
    FTM = {
        /// FlexTimer module.
        ///
        /// This is a timer module
        0x0  => reg32 SC  /// Status and control register
        {
             0..2 => PS,           /// Prescale
             3..4 => CLKS
             {
                 0x0 => NO_CLOCK,     /// no clock selected
                 0x1 => SYSTEM_CLOCK, /// use system clock
                 0x2 => FIXED_FREQ,   /// use fixed frequency clock
                 0x3 => EXTERNAL,     /// use external clock
             },
             5    => CPWMS,
             6    => TOIE,
             7    => TOF: ro,
        },
    
        0x4  => reg32 CNT /// Count register
        {
            0..15 => COUNT,
        },
    
        0x8  => reg32 MOD /// Modulo register
        {
            0..15 => MOD,
        },
    
        0xc  => group CH[8]                 /// Compare/capture channels
        {
            0x0 => reg32 CSC                /// Compare/capture channel status and control register
            {
                0 => DMA,
                2 => ELSA,
                3 => ELSB,
                4 => MSA,
                5 => MSB,
                6 => CHIE,
                7 => CHF,
            },
    
            0x4 => reg32 CV                 /// Channel counter value
            {
                0..15 => VAL,
            },
        },
    
        0x4c => reg32 CNTIN                 /// Counter initial value register
        {
            0..15 => INIT,
        },
    
        0x50 => reg32 STATUS                /// Channel status register
        {
            0..7 => CHF[8],                 /// Channel flags
        },
    }
)
```
which should produce something like,
```rust
pub struct FTM_SC     { _value: VolatileCell<u32> }
pub struct FTM_CNT    { _value: VolatileCell<u16> }
pub struct FTM_MOD    { _value: VolatileCell<u16> }
pub struct FTM_CNTIN  { _value: VolatileCell<u16> }
pub struct FTM_STATUS { _value: VolatileCell<u8> }

#[allow(uppercase_variables)]
pub struct FTM {
    pub SC: FTM_SC,
    _pad0: [VolatileCell<u8>, ..1],
    pub CNT: FTM_CNT,
    _pad1: [VolatileCell<u8>, ..1],
    pub MOD: FTM_MOD,
    pub CH: [Channel, ..7],
    _pad2: [VolatileCell<u8>, ..2],
    pub CNTIN: FTM_CNTIN,,
    _pad3: [VolatileCell<u8>, ..3],
    pub STATUS: FTM_STATUS
}

impl FTM_SC {
    pub fn set_PS(value: uint) {
        self.value.set((self.get_PS() & !0b111) | (&0b111 & val as u32) << 0);
    }
    pub fn get_PS() -> uint {
        (self.value.get() >> 0) & 0b111
    }
    ...
}

impl FTM_CNT { ... }
impl FTM_MOD { ... }
impl FTM_CNTIN { ... }

impl FTM_STATUS {
    pub fn set_CHF(n: uint, value: bool) { .. }
    pub fn get_CHF(n: uint) -> bool { ... }
}

#[allow(uppercase_variables)]
pub struct Channel {
    _CSC: VolatileCell<u32>,
    _CV:  VolatileCell<u32>,
}

impl Channel { ... }
```

## Lowering semantics

Lowering the DSL representation to a Rust data structure would be performed as follows,

  * For a register group `GROUP` produce a type `pub struct GROUP { ... }`
    where the fields are generated as follows,

    * For each register `REG` in the group,
      * If the register has a group type `T`, produce a field `pub REG: T`
      * If the register has an array group type `T[N]`, produce a
        field `pub REG: [T, ..N]`
      * If the register has a primitive type `T` or `T[N]`, produce a type
        `pub struct GROUP_REG {_value: VolatileCell<T>}` and,
        * If the register has an array type `T[N]`, produce a field
          `pub REG: [GROUP_REG, ..N]` in `struct GROUP`
        * Otherwise, produce a field `pub REG: GROUP_REG` in `struct GROUP`
      
To generate the accessor functions, the following lowering would be performed,

  * For a register group `GROUP`,
    * For each register `REG` in the group,
      * For each field `FIELD` of the register,
        * If the field has array type `T[N]`, produce accessors
  ```rust
  pub fn get_FIELD(n: uint) -> T { ... }
  pub fn set_FIELD(n: uint, value: T) { ... }
  ```

        * Otherwise produce accessors
  ```rust
  pub fn get_FIELD() -> T { ... }
  pub fn set_FIELD(value: T) { ... }
  ```