radeonsi: simplify constant buffer upload for big endian

Point util_memcpy_cpu_to_le32 to a buffer storage directly.

v2: simplify more

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
gallium/radeon: Set gpu_address to 0 if r600_virtual_address is false

Without this patch I get the following during DMA transfers:
[drm:radeon_cs_ib_chunk] *ERROR* Invalid command stream !
radeon 0000:01:00.0: CP DMA dst buffer too small (21475829792 4096)

This is a fixup for e878e154cdfd4dbb5474f776e0a6d86fcb983098.

Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
tgsi/ureg: add ureg_UARL shortcut
mesa,gallium: API settings / rasterization rules
gallium,drivers: use API settings / rasterization rules

v2: compilation fixes by David Heidelberger <david.heidelberger@ixit.cz>
v3: compilation fix by Thermionix <bond711@gmail.com>
nv50,nvc0: handle TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
nv50,nvc0: handle NULL vertex elements without fallback
nv50/ir/tgsi: implement TGSI_OPCODE_NRM,DP2A

Used by d3d9 st.
nv50: don't emit buffer for skipped vertex elements

Grr, should forbid that and insert dummy elements in nine.
nvc0: avoid fault in get_query_result if there was no begin_query
gallium,drivers: add PIPE_CAP_DEVICE_MEMORY_SIZE

Signed-off-by: David Heidelberger <david.heidelberger@ixit.cz>
winsys/sw/wrapper: hook up is_displaytarget_format_supported

Looks like no one's using this thing.
gallium/draw: support hack to disable clipping
nv50: support for hackish viewport bypass
nv50,nvc0: d3d9 requires transfer stride to be aligned to 4
gallium: add blending to pipe blit
nvc0: use blending to pipe blit
mesa/st: initialize blit.alpha_blend
nvc0: NULL vertex buffers are allowed
nv50/ir/tgsi: handle TGSI_OPCODE_CND