Revert "bump l2 a bit for touchboost freq"

This reverts commit d2dace01c54a429218f07086f86334dda766bed1.
Revert "Reduce number of cpu frequencies"

This reverts commit 19607c55bfb1746815e5e70f1dbf05be42eb3804.
Revert "More overclocking options"

This reverts commit 46a581b639b2c975c6ce0d0c16afbc6101526207.
Revert "L2 cache and bus bandwidth overclocking"

This reverts commit 431d9f1909163418605f93eb03f854e060a2eb55.
Revert "CPU overclocking"

This reverts commit a6bbdf13be80e15d2eb85541633bb5599bcbc1d7.
Revert "Increase voltage limits"

This reverts commit f256d8636bac3cdb51edd256b09575f0ab99c5cc.
Revert "Voltage Control: add sysfs interface"

This reverts commit 806e43b3b01d2e953260fb0e65ef5360733b160c.
Revert "Voltage Control: initial voltage control for MSM Snapdragon 800 SOC"

This reverts commit 9376a61ea737619f7f2c14b2d0111565dd4067ed.

Conflicts:
	arch/arm/mach-msm/acpuclock-krait.c
sound: Export effects header to userspace

Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
ARM: mm: implement LoUIS API for cache maintenance ops

ARM v7 architecture introduced the concept of cache levels and related
control registers. New processors like A7 and A15 embed an L2 unified cache
controller that becomes part of the cache level hierarchy. Some operations in
the kernel like cpu_suspend and __cpu_disable do not require a flush of the
entire cache hierarchy to DRAM but just the cache levels belonging to the
Level of Unification Inner Shareable (LoUIS), which in most of ARM v7 systems
correspond to L1.

The current cache flushing API used in cpu_suspend and __cpu_disable,
flush_cache_all(), ends up flushing the whole cache hierarchy since for
v7 it cleans and invalidates all cache levels up to Level of Coherency
(LoC) which cripples system performance when used in hot paths like hotplug
and cpuidle.

Therefore a new kernel cache maintenance API must be added to cope with
latest ARM system requirements.

This patch adds flush_cache_louis() to the ARM kernel cache maintenance API.

This function cleans and invalidates all data cache levels up to the
Level of Unification Inner Shareable (LoUIS) and invalidates the instruction
cache for processors that support it (> v7).

This patch also creates an alias of the cache LoUIS function to flush_kern_all
for all processor versions prior to v7, so that the current cache flushing
behaviour is unchanged for those processors.

v7 cache maintenance code implements a cache LoUIS function that cleans and
invalidates the D-cache up to LoUIS and invalidates the I-cache, according
to the new API.

Reviewed-by: Santosh Shilimkar <santosh.shilimkar@xxxxxx>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>

Signed-off-by: Paul Reioux <reioux@gmail.com>
ARM: kernel: update cpu_suspend code to use cache LoUIS operations

In processors like A15/A7 L2 cache is unified and integrated within the
processor cache hierarchy, so that it is not considered an outer cache
anymore. For processors like A15/A7 flush_cache_all() ends up cleaning
all cache levels up to Level of Coherency (LoC) that includes
the L2 unified cache.

When a single CPU is suspended (CPU idle) a complete L2 clean is not
required, so generic cpu_suspend code must clean the data cache using the
newly introduced cache LoUIS function.

The context and stack pointer (context pointer) are cleaned to main memory
using cache area functions that operate on MVA and guarantee that the data
is written back to main memory (perform cache cleaning up to the Point of
Coherency - PoC) so that the processor can fetch the context when the MMU
is off in the cpu_resume code path.

outer_cache management remains unchanged.

Reviewed-by: Santosh Shilimkar <santosh.shilimkar@xxxxxx>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>
Signed-off-by: Paul Reioux <reioux@gmail.com>
ARM: kernel: update __cpu_disable to use cache LoUIS maintenance API

When a CPU is hotplugged out caches that reside in its power domain
lose their contents and so must be cleaned to the next memory level.

Currently, __cpu_disable calls flush_cache_all() that for new generation
processor like A15/A7 ends up cleaning and invalidating all cache levels
up to Level of Coherency, which includes the unified L2.

This ends up being a waste of cycles since the L2 cache contents are not
lost on power down.

This patch updates __cpu_disable to use the new LoUIS API cache operations.

Reviewed-by: Santosh Shilimkar <santosh.shilimkar@xxxxxx>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>
Signed-off-by: Paul Reioux <reioux@gmail.com>
ARM: mm: update __v7_setup() to the new LoUIS cache maintenance API

The ARMv7 processor setup function __v7_setup() cleans and invalidates the
CPU cache before enabling MMU to start the CPU with a clean CPU local cache.

But on ARMv7 architectures like Cortex-[A15/A8], this code will end
up flushing the L2 caches(up to level of Coherency) which is undesirable
and expensive. The setup functions are used in the CPU hotplug scenario too
and hence flushing all cache levels should be avoided.

This patch replaces the cache flushing call with the newly introduced
v7 dcache LoUIS API where only cache levels up to LoUIS are cleaned and
invalidated when a processors executes __v7_setup which is the expected
behavior.

For processors like A9 and A5 where the L2 cache is an outer one the
behavior should be unchanged.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@xxxxxx>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>
Signed-off-by: Paul Reioux <reioux@gmail.com>
Revert "msm: lpm_resources: Ignore RPM notifications only during RPM PC."

This reverts commit 06b0425ff9f6962d176d5c9054b8d364cd282630.

Signed-off-by: flar2 <asegaert@gmail.com>
msm: pm-8x60: Register sleep status driver before regulator

During hotplug, drivers wait for core to be power collapsed to turn off
the resources used by a core in CPU_DEAD notification. The kernel
thermal module which hotplugs the core in certain conditions is
registered in the arch_initcall(). To ensure that the CPU_DEAD waits for
sleep status to be set during hotplug, register the cpu sleep status
driver before the regulator driver.

To this effect, the sleep status driver is no longer made a child device
for pm-8x60 device.

Change-Id: I772521f4b3cd18e367aa44a41d60ef9735c99ef9
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
Signed-off-by: flar2 <asegaert@gmail.com>
msm: lpm: Alter the voting mechanism for lpm drivers

Currently the power management drivers monitor the sleep votes received
for certain system wide resources such as system clock and digital voltage
rail. By knowing the sleep vote and the available sleep time , latency
requests the low power management drivers (lpm_resources module) can alter
the sleep votes for those resources during RPM notified sleep modes.

Changing this method because this method requires a new low power level be
added for each combination of the system wide resources being monitored
and that each level be characterized (latency, power etc), this method is
not very scalable as the number of system resources being monitored by the
low power management driver increases. But most of all the decisions on
whether there is enough sleep time to enter these system wide sleep modes
(residency decisions) need to be made at RPM.

This change will remove the lpm_resources module altogether and remove all
low power levels beyond those pertaining L2 cache at lpm_levels.

CRs-Fixed: 490824
Change-Id: I255b696851074dcf7bed40b648c0eb3c5c4d0d6d
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
Signed-off-by: flar2 <asegaert@gmail.com>
msm: lpm_levels: Adjust latency for Multi core cases

In multi core cases for several cores going in and out of power collapse
the warmboot is serialized at Trust Zone, which means the exit latency
will scale based on the number of cores exiting power collapse.

Adjust for this when chosing a low power mode based on the number of online
cpus.

Change-Id: I4fe137a1bf8596b7da7990845b18ceb8f3d529da
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
Signed-off-by: flar2 <asegaert@gmail.com>
msm: clock: Keep proper track of current voltage level

Fix a bug where vdd_class->cur_level is not updated when regulator api
calls are successful. The impact of the bug is unnecessary calls to
regulator APIs but not additional RPM calls since the regulator APIs
will optimize out repeated requests for the same voltage/current.

In case the regulator APIs fail, this bug might also result in
undervolting. But that's an unlikely case in a real product.

Change-Id: Ibe3574b6b72fcf898a5bfe9b5b253a8d0e0125ae
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
Signed-off-by: flar2 <asegaert@gmail.com>
hammerhead: Updates for recent PM changes

Change-Id: I94ebd3376c990879cd6ca0a140ff8c102b567acb

Signed-off-by: flar2 <asegaert@gmail.com>
msm: spm: Replace msm_spm_apcs_set_vdd with msm_spm_set_vdd

msm_spm_apcs_set_vdd() is used to set the vdd of a gang rail through the
L2 SAW2. Remove this api and overload the msm_spm_set_vdd() call with a
dont-care 'cpu' argument instead.

Detect if the target is configured to use L2 SAW as APCS master using a
boolean property in the device tree.

Change-Id: Ib8d9605474fa44d5223985ec8cb1040cde230592
Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>
Signed-off-by: flar2 <asegaert@gmail.com>