arm: mm: Account for lowmem in the static vm

Linux page directory size differs from the ARM section size used
for lowmem mappings (2MB vs. 1MB). The ioremap code takes this
into account when static mappings are set up and pads PMD sections
accordingly. Lowmem needs to be tracked in the static mappings as
well to account for the size difference as well. If the lowmem
is not tracked, we may attempt to use part of an address range that
should be reserved which can trigger BUGs() or unexpected faults.

Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>

Conflicts:
	arch/arm/mm/ioremap.c
	arch/arm/mm/mmu.c
ARM: 7691/1: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead

Many ARMv7 cores have hardware page table walkers that can read the L1
cache. This is discoverable from the ID_MMFR3 register, although this
can be expensive to access from the low-level set_pte functions and is a
pain to cache, particularly with multi-cluster systems.

A useful observation is that the multi-processing extensions for ARMv7
require coherent table walks, meaning that we can make use of ALT_SMP
patching in proc-v7-* to patch away the cache flush safely for these
cores.

Reported-by: Albin Tonnerre <Albin.Tonnerre@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>

Conflicts:
	arch/arm/include/asm/tlbflush.h