[DDR core]: Fix Read Leveling calibration - as per #AR 55531
hdl/modules/*/*/wb_fmc130m_4ch.vhd: add RAMP test data to FMC130M output

On writing to the corresponding register field, we enable the RAMP
test data. Previously, only the WBS interface had this option, not
the standard interface.
hdl/modules/*/fmc_adc_clk.vhd: fix VAR_LOAD CLOCK delay

The "ce" signal of the IDELAYE2 primitive was hardcoded to '1'.
Clearly a bug when using the primitive in VAR_LOAD mode for Xilinx
7SERIES FPGAs. The correct value is '0' as the "ld" signal controls
"valid" delay value.

With the "ce" signal alwas on, we would have, on each clock cycle,
an increment in the delay value causing sampling errors.

This fixes #38 github issue.