sync interactive with cod2nxp
set min battery level to 1
OMAP4: EMIF: Added timings for 466MHz elpida lpddr2 memory

OMAP4470 support 466MHz DDR2 memory. This patch add timings from
datasheet for EDB8164B3PF.

Change-Id: Ief7520719a2d7ec3dc9c93a3ecbfcef7cf64507c
Signed-off-by: Vitaly Chernooky <vitaly.chernooky@ti.com>
OMAP4470: Memory timings fix for LPDDR2 466 MHz

Fixed memory timings for LPDDR2 466MHz according to
hardware recommendations.

Change-Id: I07e821c8fafc1b559b61a443083fc9c1acddc87a
Signed-off-by: Mykola Oleksiienko <x0174904@ti.com>
OMAP4470 LPDDR interface configuration update for 466MHz

Some instability with OMAP4470 when running the DDR at 466MHz is
discovered. This instability is resolved with updated LPDDR settings:

- DLL delay should be set to 461ps:
  DDR_PHY_CTRL_1_SHDW[11:4] = 0x37

- Read latency should be set to 0xB:
  DDR_PHY_CTRL_1_SHDW[3:0] = 0xB

- Slew Rate should be set to “FASTEST” and Impedance Control to “Drv12”:
  CONTROL_LPDDR2IOx_2[LPDDR2IO1_GR10_SR] = 0
  CONTROL_LPDDR2IOx_2[LPDDR2IO1_GR10_I] = 7
  where x=[1-2]

Change-Id: Ifa47a7ccae437225db5838039e528c04250a911d
Signed-off-by: Volodymyr Mieshkov <volodymyr.mieshkov@ti.com>

Conflicts:
	arch/arm/mach-omap2/pm44xx.c
ram timing optimize
optimize 466 timings